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Many, many, many publications on this if you cared to
investigate.
Simple advice - forget the voltage, think about the current
loops (there are 2*N*(N-1) permutations of these in pin-pin
ESD testing - polarity times entry times exit pin) and how
you will return the current to its source with as little loss
in the chip as possible.
Everything after that is details of art, implementation and
element ruggedness. Enjoy.
This is a very wide and deep area, ESD protection...
Very briefly - at the IC level, pins are protected by on-chip ESD elements (ESD diodes, clamps - MOSFETs, SCRs (thyristors), etc.).
Connections to these elements should be low-resistive and minimizing current density, for current levels of the order of 1.0 - 20.0 Amps.
On-chip ESD protection should protect the IC from various types of ESD stress conditions (different time-dependent waveforms) - HBM, CDM, MM, ...
Various standards describe how the stress conditions are applied to test the ESD protection.
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