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[SOLVED] Verilog Code giving wrong output for subtraction / -1 * number

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rahdirs

rahdirs

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Hi,

I am trying to do the following in Verilog: if count < 8, pass the i/p to o/p, else multiply the i/p by -j. Note: i/p is a complex number.

My code:

Code: 
always @(count,out2_complex_bf1,out2_real_bf1) begin
if (count >= 4'b1000) begin
	out2_real_bf1_t 		<= out2_complex_bf1;
	out2_complex_bf1_t 	<= (~(out2_real_bf1)) + 1;
end else
	out2_real_bf1_t 		<= out2_real_bf1;
	out2_complex_bf1_t 	<= out2_complex_bf1;	
end

I tried doing
Code: 
out2_complex_bf1_t 	<= (~(out2_real_bf1)) + 1;
by just putting -(out2_real_bf1). But o/p is all 0. I have attached the waveform.

Capture.JPG
 

Is the missing begin a typo? As written above you have the following code:

Code Verilog - [expand]
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always @(count,out2_complex_bf1,out2_real_bf1) begin
 
  if (count >= 4'b1000) begin
    out2_real_bf1_t    <= out2_complex_bf1;
    out2_complex_bf1_t <= (~(out2_real_bf1)) + 1;
  end else
    out2_real_bf1_t    <= out2_real_bf1;
 
 
  out2_complex_bf1_t <= out2_complex_bf1;  
 
end


So the simulation is showing exactly what you wrote, assign out2_complex_bf1 to that ..._t version on every clock after the count goes over 8 as you replace the first assignment is overwritten.

BTW use the @* instead of writing out all the signals, less likely to make a mistake and end up with simulation synthesis mismatches.
 

ads-ee said:
Is the missing begin a typo? As written above you have the following code:

Code Verilog - [expand]
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always @(count,out2_complex_bf1,out2_real_bf1) begin
 
  if (count >= 4'b1000) begin
    out2_real_bf1_t    <= out2_complex_bf1;
    out2_complex_bf1_t <= (~(out2_real_bf1)) + 1;
  end else
    out2_real_bf1_t    <= out2_real_bf1;
 
 
  out2_complex_bf1_t <= out2_complex_bf1;  
 
end


So the simulation is showing exactly what you wrote, assign out2_complex_bf1 to that ..._t version on every clock after the count goes over 8 as you replace the first assignment is overwritten.

BTW use the @* instead of writing out all the signals, less likely to make a mistake and end up with simulation synthesis mismatches.
Click to expand...


I understood the error, there was a missing end .. statement. Not sure why it didn't raise an error
Code Verilog - [expand]
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always @(count,out2_complex_bf1,out2_real_bf1) begin
 
  if (count >= 4'b1000) begin
    out2_real_bf1_t    <= out2_complex_bf1;
    out2_complex_bf1_t <= (~(out2_real_bf1)) + 1;
  end else begin
    out2_real_bf1_t    <= out2_real_bf1;
    out2_complex_bf1_t <= out2_complex_bf1;  
  end
end
 
Last edited:

It isn't an error, notice ads_ee's post that has the correct indentation.
 

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