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connection issue in common centroid

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diego.fan

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Hi, may I ask a question about the connection of common centroid? I worked as radio frequency Engineer (1~2GHz)before. We never cross two RF traces in adjacent metals and always use a ground between them.

Now I'm doing the layout of IC with tens of KHz. I search in this forum and found many people suggest common centroid to do the matching, especially in input differential pair.

But common centroid has a big problem in connection. Too many lines cross coupling. First question: I don't know what's effect it will cause? only more parasite coupling to slow the speed? In RF if this condition happens, we will see a big problem in EMC and intermodulation.

Second question: For example, I make a draft drawing on the below pattern. Do you has some good ways to arrange these lines?
ABBAABBA
BAABBAAB
BAABBAAB
ABBAABBA

questions.png

However Interdigitated is not suitable for me because my transistor width is a little long, it will be a lonnnnnnnng line if Interdigitated is used.
 

You can always add a cap into your schematic and simulate its effect. In the case of an RF VCO it is tolerable (the tank cap will be a bit higher), so even in RF there is no hard rules for that.
In the kHz regime you can forgot the capacitances, but make sure you are there. In a diff pair you gain more in terms of CMRR, PSRR and kickback if you use a symmetrical structure.
If the wiring is messy, than consider using a bigger unit.
 

First of all, the source connections should has the same length connected to common point.
The proper 2D common centroid should not generate too much crossing between drain paths.
 

Are you really layout area sensitive? Are you constrained
to use only the bottom two or three routing layers?
What is the relative penalty of looser layout and less
lateral coupling, vs the increased substrate coupling
of longer lines? These are for you to consider for style.

If you want to drive down capacitance use a (say)
via1, met2, via2 stacked "pillar" at (say) the north
end of A and the south end of B fingers, run the trace
E-W and you have only orthogonal intersection fringing
coupling across a fatter dielectric; A and B traces are
separated by finger W less the "pillar" width.
 

You can always add a cap into your schematic and simulate its effect. In the case of an RF VCO it is tolerable (the tank cap will be a bit higher), so even in RF there is no hard rules for that.
In the kHz regime you can forgot the capacitances, but make sure you are there. In a diff pair you gain more in terms of CMRR, PSRR and kickback if you use a symmetrical structure.
If the wiring is messy, than consider using a bigger unit.

Thanks,tzg6sa. "even in RF there is no hard rules for that.": Do you you mean in RF, it's unnecessary to put ground on the left ,right, bottom top of the RF trace? Just like using a box of ground to around the RF trace. If two RF traces are parallel or orthogonal couple with each other, how to avoid signal affect from one trace to another?

- - - Updated - - -

First of all, the source connections should has the same length connected to common point.
The proper 2D common centroid should not generate too much crossing between drain paths.

Yes, you are right. I fine tune it, now it has no more than 3 layers of metal orthogonal overlap with each other. I cannot decrease overlap further..
Otherwise, more traces will go round the outside, I think it will increase trace length too much.

- - - Updated - - -

If you want to drive down capacitance use a (say)
via1, met2, via2 stacked "pillar" at (say) the north
end of A and the south end of B fingers, run the trace
E-W and you have only orthogonal intersection fringing
coupling across a fatter dielectric; A and B traces are
separated by finger W less the "pillar" width.

Thanks, dick, could you please explain it more. I don't understand.
 

Thanks,tzg6sa. "even in RF there is no hard rules for that.": Do you you mean in RF, it's unnecessary to put ground on the left ,right, bottom top of the RF trace? Just like using a box of ground to around the RF trace. If two RF traces are parallel or orthogonal couple with each other, how to avoid signal affect from one trace to another?

I said, that it is not always necessary. If the cross coupled transistors of a VCO have parasitic cap, then it is not the end of the word, it just means that it will participate to your tank capacitance.
An inductor is also just a trace, but you do not have walls around it. If you want to control the environment with ground shields, than you have a transmission line. Inductors are used often in RF circuits.
 
Here is a simple (not optimized, without dummies but ensure proper source connections) common centroid layout draft. There are only two crosses between drain paths.

common_centroid.png
 

Here is a simple (not optimized, without dummies but ensure proper source connections) common centroid layout draft. There are only two crosses between drain paths.

View attachment 138699

Thanks,it looks nice. But how to deal with gates? I tried to draw, but it will like below. It's hard to avoid overlap in the green area.
common_centroid.png
 

It is not hard to avoid crossing between gates, it is very easy. E.g. by putting horizontal 1st metal paths between mosfets and connecting the gates with short vertical paths to these ones. Do not worry about M2-M1 gate-to-source parasitics (cap density of oxide is much higher), while drain-to-gate M3-M1 is even less.
The most important is to minimize parcaps between differential paths.
 
It is not hard to avoid crossing between gates, it is very easy. E.g. by putting horizontal 1st metal paths between mosfets and connecting the gates with short vertical paths to these ones. Do not worry about M2-M1 gate-to-source parasitics (cap density of oxide is much higher), while drain-to-gate M3-M1 is even less.
The most important is to minimize parcaps between differential paths.

Thanks, this is a really nice suggestion. I extend your answer, I think the overlapping lines between G-D and G-S can be neglected compared to the capacitance in oxide. It means If I cannot avoid overlap, I can choose G-D or G-S overlapping. But D-D or S-S overlap should be avoided, is that right? Because less Oxide on D and S.

For the differential paths, this suggestion really conflicts with my past experience on RF board layout(not IC). When we draw differential lines before, we often put them in parallel, keep the distance between two lines: 1~2 times of width of lines. It means the distance between centrelines of these differential lines should be 2W--3Width.

But this way means the coupling between differential lines should be big. So how to deal with differential paths in IC? as far a possible or follow 3W rule.
 

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