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[SOLVED] Synthesizing clk delay : Verilog functional code

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ashrafsazid

ashrafsazid

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Hi Altruists,

Can anybody please suggest me how can I make a quarter cycle "synthesized" delay as like as the figure below?

clk_del.PNG

The clock pulses here have a period of 200ns. The behavioral Verilog code was written by assigning a #delay to the signal. As like as below:

`timescale 1ns/1ps

@(posedge main_clk) begin

clk_violet = high
clk_orange = #50 high

But I cannot solve it out to make a delay with synthesizable code. Please help.
 

The usual way to implement this kind of delays is a PLL or DLL, depending on the available resources of your hardware.
 

1. You want to keep the clock period
2. You want to change the phase.
3. You only have the one clock.

I don't know of an RTL way to achieve this, but their are macros/cores within the IC device(FPGA I assume) that you can utilize as #2 mentioned

If you had a significantly faster clock, you could sample the slower clock. Delay it by so many fast clock cycles & that way it appears as if the cycle has shifted.
 

What do you think about that:

1. Take 10 MHz clock (100 ns period)
2. Invert it - you will get 2nd clock 10 MHz phase shifted by 180 deg.
3. Use Dff to divide those two signals by 2.
4. You will get two signals at 5 MHz (200 ns period) shifted by 90 deg -> that is 1/4th of cycle.

But phase relations might be lost due to delays.
 

Use a delay element, which should be a FPGA primitive.
I also also don't know how to do it in RTL (if the last sentence in #3 cannot be applied).
Eg for a Xilinx 7 series FPGA, I would instantiate the IDELAY/ODELAY primitives to achieve the desired # amount.
 

ashrafsazid said:
Hi Altruists,

Can anybody please suggest me how can I make a quarter cycle "synthesized" delay as like as the figure below?

View attachment 138658

The clock pulses here have a period of 200ns. The behavioral Verilog code was written by assigning a #delay to the signal. As like as below:

`timescale 1ns/1ps

@(posedge main_clk) begin

clk_violet = high
clk_orange = #50 high

But I cannot solve it out to make a delay with synthesizable code. Please help.
Click to expand...

200ns is so slow that you could use a third clock to define these two. you need a precision of 50ns only, which is still very slow even for older FPGAs.

If your clock periods were more challenging, PLLs would be the way to go.
 

Thanks everyone for your support. I solved it by using a faster clock and using some logic .
 

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