How to implement "latch-up" guard rings and prevent parasitic lateral NPN at the same

How to implement "latch-up" guard rings and prevent parasitic lateral NPN at the same

Hi all.
I am trying to create latch-up guard rings for IO "low-side" BJT_36V and HVNMOS_36V according to TSMC BCD 0.18 design rule.
And there is a requirement of design rule to keep huge space between two Nwells connected to two different pads to prevent parasitic NPN. Space is so great (50um) that the very idea of creating rings seems impracticable.
Please see the picture.



If I use smaller distance I get DRC violations.

I don't know is it really possible to be turned on for this parasitic transistor in some the worst coincidence, so I am not sure if I can waive such DRC violations and use acceptable dimensions.

Please advice!

Re: How to implement "latch-up" guard rings and prevent parasitic lateral NPN at the

mult said:

Space is so great (50um) that the very idea of creating rings seems impracticable.

If I use smaller distance I get DRC violations.

Click to expand...

That's probably the min. distance between pads. What if you insert a p⁺ guardRing in between? Does the same design rule take effect? Can you find & show the text of the design rule responsible for this violation?

Re: How to implement "latch-up" guard rings and prevent parasitic lateral NPN at the

You can't "get rid of" parasitic BJTs in junction isolated
technologies. What you can do is (a) degrade the hFE
to where any SCR can't hold and (b) shunt the base to
that any SCR can't fire with any sane current injection
(this may be complemented by spec limitations on pin
currents, switch-node dV/dt, and so on - but these
had better be non-problematic to the user of the
device, their normal and abnormal conditions).

There ought to be detailed latchup design rules
and, you'd think, PCell switches (or rings built in,
that you don't get to mess with) in a well done
PDK.

Re: How to implement "latch-up" guard rings and prevent parasitic lateral NPN at the

erikl said:

What if you insert a p+ guardRing in between? Does the same design rule take effect? Can you find & show the text of the design rule responsible for this violation?

Click to expand...

There is a special section in design rule called "Parasitic ESD Rule": "The Rule defines the minimum spacing between two n-type regions to prevent parasitic lateral npn from turning on and unexpected ESD failure"
Here is the basic rule:
"Minimum space between two HVNW connected to different potential PADs ...(conditions such as HV, presence of N buried layer, etc)... 50 um;
If the n-type regions are connected to PADs with same logic or power state, this violation can be waived."
Yes, even with using of p+ guard ring the same design rule take effect.
I explain the structure of rings in the picture.

dick_freebird said:

There ought to be detailed latchup design rules
and, you'd think, PCell switches (or rings built in,
that you don't get to mess with) in a well done
PDK.

Click to expand...

You are right, there is a switch so-called "Sandwich Ring" in some of Pcells. But I think that is not exactly what is needed.
Please see the picture.
This switch adds N and P guard rings and extends NBL to the outer Nwell. Thus this N ring cannot be connected to potential other than PAD. But it doesn't make sence to connect N guard ring to not the most positive potential if the purpose is latch up prevention.

Re: How to implement "latch-up" guard rings and prevent parasitic lateral NPN at the

mult said:

If the n-type regions are connected to PADs with same logic or power state, this violation can be waived."

Click to expand...

Is the VDD pad (always the left one in your pictures) used as a VDD supply pad, or is it just the connection of the n-well guard ring? In the latter case you could of course connect the 2 pads and waive the DRC violation.

Re: How to implement "latch-up" guard rings and prevent parasitic lateral NPN at the

Yes, "connected" ought to mean the supply pad makes
the rule work. However, if the cell is being verified at a
level lower than chip top level, maybe this pad is not
in the layout. In such a case maybe you need to add a
"frame" which has all supply pads (but as little else as
necessary) to validate the cell will not show errors once
embedded in its final home.

It might also be possible to spoof the rules by (say)
putting a 1x1um rectangle of M6Pad (or whatever -
parse the DRC rules backward to find what "connected"
means, to the rules set) on the supply lines.

Re: How to implement "latch-up" guard rings and prevent parasitic lateral NPN at the

erikl said:

Is the VDD pad (always the left one in your pictures) used as a VDD supply pad, or is it just the connection of the n-well guard ring? In the latter case you could of course connect the 2 pads and waive the DRC violation.

Click to expand...

VDD is supply pad, and VDD is used to connect N Latchup ring as the highest voltage of the chip.

Re: How to implement "latch-up" guard rings and prevent parasitic lateral NPN at the

mult said:

Space is so great (50um) that the very idea of creating rings seems impracticable.

Click to expand...

Ok. Can't you connect the n-well guardRing directly to the IO-pad (the right one), and position the VDD-pad (used as power supply pad only) farer away?

It isn't necessary to use a higher n-well guardRing voltage than the (instantaneous) voltage of the pad which shall be protected.