Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Create test vectors from real world signals

Status
Not open for further replies.

matrixofdynamism

Advanced Member level 2
Joined
Apr 17, 2011
Messages
593
Helped
24
Reputation
48
Reaction score
23
Trophy points
1,298
Activity points
7,681
What is the simplest way to record signals using an oscilloscope or logic analyzer and then use them to create test vectors for a VHDL/Verilog design?
 


What is the simplest way to record signals using an oscilloscope or logic analyzer and then use them to create test vectors for a VHDL/Verilog design?

can your scope dump information into a file (CSV-like, maybe?) ? I would write a testbench that parses the scope output file and makes a simulation environment out of it.
 

can your scope dump information into a file (CSV-like, maybe?) ? I would write a testbench that parses the scope output file and makes a simulation environment out of it.

Funny you should mention this...I'm doing that right now in my current testbench :)

Not for the timing but it's got my data in it.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top