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how to select Output Capacitor in Booster?

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parachutes30

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This is from Ti TPS40210 datasheet。
but I couldn't understand there is a "8" before Iout x Ton / Vripple。
捕获.PNG
 

Hi,

I think it's possibly the 8Vin min. they use for the whole design procedure, in table 1 on page 25.
 

d123 said:
I think it's possibly the 8Vin min.
Click to expand...
That "8" is dimensionless.. so it is not a voltage.
You can ask yourself the same question for the ESR: why 7/8 ?
Same for Cin: why 4 multiplies Vin ripple ?

Probably are some values for safety margins Texas Instruments arrived to in their years of experience designing stuff.
 
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Please my friend, do not use such formulae for capacitor ripple in output of boost...use the formula as follows.........ac(rms) ripple = sqrt(irms^2 - idc^2)

where
irms = the rms current coming out of the boost diode
idc = the dc output current of the boost.

....the above two things are easily found frm standard trapezoid wave eqautions.....
i post them here, the trapezoid equations are in there

(but also here
www.oocities.org/capecanaveral/lab/9643/rms.htm
)

if doing regular hardswitched smps regularly , you must please use trapezoid equations...it takes too long too keep doing the integration every time.
 

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Here is the eqaution for IRMS of a trapezoid current waveform

IRMS = SQRT[D * (I1^2 + I1.I2 + I2^2)/3]

where D = duty
I1 = the only thing it can be in that equation
I2 = ditto

This is one of the most key waveforms in hard switched SMPS as you know.
And a triagle wave is just a trapezoid with one side zero
A square wave is just a trapezoid with 2 sides equal.

...so its good for tri's and squares too.

NOT worth doing the integration every time...just see the equation.
 

OK!
I can understand that setting 8 mulitpler cap is to allow for a load transient.
So do you agree if we don't need to consider load transient, can I omit this "8"?
 

After carefully reading this document form TI, I think a bulk electrolytic cap is only for transients and ceramics is very one that for reducing the ripple.
Like the TPS40210 picture, TI designer seems always use a parallel combination of electroytic and ceramic.

https://www.ti.com/lit/an/slta055/slta055.pdf
 
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