Which is a better way of inputting an FSM

Code VHDL - [expand]
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-- This file was generated by               
-- Qfsm Version 0.54                    
-- (C) Stefan Duffner, Rainer Strobel           
 
-- Inputs:   x
-- State/Output y
-- State_0      0 
-- State_1      0 
-- State_2      0 
-- State_3      1 
 
LIBRARY IEEE;
 
USE IEEE.std_logic_1164.ALL;
 
ENTITY FSM IS
  PORT (clk: IN std_ulogic;
        rst_n: IN std_ulogic;
        x: IN std_ulogic;
        y: OUT std_ulogic;
        debug_state: OUT std_ulogic_vector (1 DOWNTO 0));
END FSM;
 
ARCHITECTURE behave OF FSM IS
 
TYPE state_type IS (State_0, State_1, State_2, State_3);
SIGNAL next_state, current_state : state_type;
 
BEGIN
  state_register: PROCESS (rst_n, clk)
  BEGIN
    IF rst_n='0' THEN
      current_state <= State_0;
    ELSIF rising_edge(clk) THEN
      current_state <= next_state;
    END IF;
  END PROCESS;
 
  next_state_and_output_logic: PROCESS (current_state, x)
    VARIABLE temp_input : std_ulogic_vector(0 DOWNTO 0);
    VARIABLE temp_output : std_ulogic_vector(2 DOWNTO 0);
  BEGIN
    temp_input(0) := x;
    CASE current_state IS
      WHEN State_0 => temp_output := "000";
        CASE temp_input IS
          WHEN "1" =>
            next_state <= State_1;
          WHEN "0" =>
            next_state <= State_0;
          WHEN OTHERS => next_state <= current_state;
        END CASE;
      WHEN State_1 => temp_output := "010";
        CASE temp_input IS
          WHEN "1" =>
            next_state <= State_1;
          WHEN "0" =>
            next_state <= State_2;
          WHEN OTHERS => next_state <= current_state;
        END CASE;
      WHEN State_2 => temp_output := "100";
        CASE temp_input IS
          WHEN "0" =>
            next_state <= State_0;
          WHEN "1" =>
            next_state <= State_3;
          WHEN OTHERS => next_state <= current_state;
        END CASE;
      WHEN State_3 => temp_output := "111";
        CASE temp_input IS
          WHEN "0" =>
            next_state <= State_2;
          WHEN "1" =>
            next_state <= State_1;
          WHEN OTHERS => next_state <= current_state;
        END CASE;
      WHEN OTHERS => temp_output := (OTHERS =>'X');
      next_state <= State_0;
    END CASE;
    y <= temp_output(0);
    debug_state <= temp_output (2 DOWNTO 1);
  END PROCESS;
 
END behave;