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Hspice Monte Carlo - Save data with veriloA script

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pcca

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Hello,

I am trying to perform some monte carlo runs in an low-voltage delta-sigma modulador using Hspice.
A verilogA script is used to save the output bitstream data in a txt file, for example 'bitstream.txt'.

I would like to know if it is possible to run monte carlo and save each monte carlo simulation in a file like: bitstrem_1.txt (for MC simulation 1), bitstream_2 (for MC simulation 2).
Is there any variable that I can use to do that?

Regards,
PCCA.
 

Not a variable, but you can make veriloga print "stuff"
to files. I know I've done it, but so long ago I forget
how, now. Recommend that each print include all of the
loop variables including MC index and seed so you can
deterministically return to any given one, should it turn
out to be "interesting".

My recollection is about a time-domain "widget" that
when placed in a circuit, would print the difference
between last zero-crossing and found zero-crossing,
do the math and stuff each found-point to a file.

Found it... $fstrobe is the command. Enjoy. Don't ask
me what %C, %I, %M are - you're on your own for book
learnin'.

I reckon you could open a unique filename each iteration
by looking at the loop variable and mashing up a filename
argument from it, rather than the single one shown here.


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// VerilogA for printFreq, veriloga
 
`include "constants.h"
`include "discipline.h"
 
module printFreq(vin,MHz);
input vin;
output MHz;
voltage vin,MHz;
integer rise;
integer out_file;
real lastrise,thisrise,freq;
 
analog begin
        @ ( initial_step ) begin
        rise=0;
                lastrise=0;
                thisrise=0;
                freq=0;
        out_file = $fopen("%C:h/printFreq_%I.csv");
//      $fstrobe(out_file,"# Generated by Spectre from instance `%M'");
                V(MHz) <+ 0;
        end
 
    @ (cross (V(vin),+1) ) begin
        rise=rise+1;
                thisrise=$abstime;
                freq=1/(thisrise-lastrise+1E-99);
                lastrise=thisrise; 
        $fstrobe(out_file, "Rise,%d,%g,%g",rise,thisrise,freq);
        end
                V(MHz) <+ freq/1E6;
 
        @ ( final_step ) begin
                $fclose( out_file );
        end
 
end
 
endmodule
 
Last edited by a moderator:
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    pcca

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Thank you dick_freebird.

I read your example and found the meaning of % I,% C, etc (listed below).

% C Design filename
% D Date (yy-mm-dd)
% H Host name
% S Simulator type
% P Unix process ID
% T Time (24hh: mm: ss)
% I Instance name
% A Analysis name

However, I was not able to use a variable to see the monte carlo iteration number and use it in the VerilogA code to change the file name.
As the goal was to run only a few simulations (up to 10) to get some idea of ​​the whole circuit performance with mismatch. I used the following strategy:

1) I define the transient simulation with monte carlo and 1 iteration:

.TRAN 100e-15 6.6e-3 START = 0.0 sweep MONTE = 1

2) At the end of the file I use the .ALTER command

.ALTER
.hdl "./veriloga_mc.va"
.OPTION SEED = 2

.ALTER
.hdl "./veriloga_mc.va"
.OPTION SEED = 3

.ALTER
.hdl "./veriloga_mc.va"
.OPTION SEED = 4

.ALTER
.hdl "./veriloga_mc.va"
.OPTION SEED = 5

With this I change the seed and start a new monte carlo simulation with 1 iteration.
In the file "veriloga_mc.va" I use the following line to create the file:

Wfile1 = $ fopen ({"bitstream_MC_% T.txt"}, "w");

So I can create different files (according to time).

It is not the best solution, but I believe that I can test the circuit under mismatch, saving the modulator bitstream in different files.
 

Perhaps at the upper levels you need to either make
the MC count and seed variables "global", or pass them
as arguments down the chain.

You might need to turn the MC number to an integer,
integer to text, concat(root,textintMC) to build filename
and like that.
 
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