When the gate voltage of a MOS capacitor is 0, why is there a depletion region?

Hi

I wonder why there is a depletion capacitance in series with Cox even when the gate voltage of a MOS cap is 0.
Books explain it with "flat band", but I want to understand it with an intuitive way.

You have the built-in charge of the gate (doping) against
the charge of the channel (doping) across the insulator.
Depending on the dopings, you could have an enhancement
mode (depleted at zero bias) or intrinsic / "zero-VT" (at
threshold, more or less, at zero bias) or depletion-mode
(an established channel, inverted near the surface, at
zero bias).

Think of the gate doping as being equivalent to a gate
voltage, across the insulator, and attracting an "image
charge" sheet to form under it. P (or positive voltage)
pulls electrons and tends to invert P- making a NMOS
channel. Dope the gate N-type (per usual practice, often
gate poly gets the same shot as S/D) and the electrons
of the body are repelled, until a positive voltage applied
to the gate overcomes that balance and attracts them.

Think back to electrostatics and the gold leaf electrometer.
How a charged object brought near its electrode, induces
an image charge. Across air or across oxide, same
difference. Except oxide "holds onto things" and has more
flaws.

That's the old-timey intuitive explanation, from before
everybody got all fancy with bands and equations and
stuff.

I have one more question.
Books don't describe depletion region when they explain the operation of MOSFET with zero gate voltage although there is a built-in voltage. What can be the reason? Is it for us not to be confused with depletion type FETs?

Every MOSFET suface slides through a continuum from accumulation
to as-doped to depletion to inversion as you increase (for NMOS)
the gate-body potential from deep negative to deep positive.

Whether this happens about zero (intrinsic / native), below zero
(depletion mode) or positive (enhancement mode) depends on
the details of fabrication.

Since enhancement mode is the dominant application (it's
a digital world, according to those who wish it so) and
since "off" operation is pretty uninteresting aside from
leakage and breakdown, you don't see much treatment of
it (and seldom even see leakage and breakdown modeled
at all, let alone well).

You have low power analog people interested in subthreshold
and about-threshold behaviors, and you have RF integration
people who like a zero-VT device or even depletion mode
ones for switch applications and PA stages that they can
run hot, not caring about whether the leakage is nA or uA
so long as they can get their on resistance, off isolation
against a 50-ohm system and so on. These two camps
will use different devices. The RF folks are the only ones
who really care to operate about Vgs=0 with an "on"
device.

Which bunch (digital, analog, RF) describes your interest?
That may lead you to references or texts.