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Flip Flop Timing Constraints

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dzafar

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Hello there,

In the image below I understand how B got its waveform.

My questions is that since C comes after an INVERTER shouldn't it have a waveform opposite to B? i.e. shouldn't it be high after the inverter delay?

Untitled.png

Thanks in advance :)
 

You are correct, the diagram shows C incorrectly. The other info is correct.
 
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    dzafar

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The diagram shows incorrect C waveform from the very beginning of the waveform...
 

@CataM, I think it doesn't matter what the waveform is BEFORE the rising edge of the clock. Correct me if I am wrong :)
 

C = not B => that does not depend on clock. Why not draw it right ? Furthermore, I believe that due to the fact that they forgot about that, they got the transition of C wrong when the clock actually applied.. which was your question.
 
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    dzafar

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I have another question,

I understand that there are two requirements for flip flop timing constraints. Setup Requirement and Hold Requirement.
I also understand that the clock speed should satisfy the following criteria: t_clk >= t_clk-to-q + t_criticalpath + t_setup.

My question is regarding the hold requirement. It says that (please refer to the image below)

Untitled.png

Q: What is t_path? Is is the critical path, the non-critical path? In short, it just not make sense to me :(

Thanks for all the wonderful help so far guys :)
 

t_path in this case is the minimum time from the register to the input of the next register. It is effectively the opposite of the critical path.

The goal is to ensure a transition can't reach the register until after t_hold.

Inside devices, hold is normally less of an issue. t_hold is often made slightly negative.

External interfaces can have any t_setup/t_hold as long as both are not negative. For example, the MIIM interface often has a hold time that is very long (> 1/2 clock cycle). There are DAC's with a negative setup time and very long hold time as well.
 

Hello there,

This is a quick question about the trade offs of the effect of optimization when we ask for a slow clock frequency.

I understand slow clock frequency leads to smaller circuits which is a good thing, right? BUT it puts more weight on optimizing logic utilization. What does this mean "putting more weight on optimizing logic utilization"?
 

dzafar said:
Hello there,

This is a quick question about the trade offs of the effect of optimization when we ask for a slow clock frequency.

I understand slow clock frequency leads to smaller circuits which is a good thing, right? BUT it puts more weight on optimizing logic utilization. What does this mean "putting more weight on optimizing logic utilization"?
Click to expand...

Not necessarily true.
The circuit built is the one that is directed from the RTL/schematic, with some optimisations based on tool settings. With a slow clock specified, it will just make it easier for the tool to meet timing. When it's fitting, it will start with a random placement, and then time it to see if it meets the spec. If it doesnt, it will try and re-route the circuit to try again. It will keep doing this until it either meets timing, or runs out of iterations.

What does this mean "putting more weight on optimizing logic utilization"?
Click to expand...

Not entirely sure, but things like register balancing and duplication will probably occur less often.
 

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