why use two DFF can decrease the possibility of Metastability?

I have two question:
1、The main way to solve the Metastability is to add a reg as a synchronizer after sampling reg
* below is my understanding, please comment in case any error:
after a long enough time, the invalid signal sampled by the sampling reg will return to an effective level, and then the synchronizer reg can take this effective level.

But returned level may be 0 or 1, then although the synchronizer reg sampled the level. That may also lead to a logical error, then what is the meaning of using the synchronizer?

2、why use two reg as synchronizer？

But returned level may be 0 or 1, then although the synchronizer reg sampled the level. That may also lead to a logical error, then what is the meaning of using the synchronizer?

Click to expand...

A double DFF synchronizer doesn't reduce the chances for meta-stability.
What it does is (dramatically) reduce the probability for the negative effects of initial meta-stability to propagate further into your design.

Regarding the output of the double DFF synchronizer - think about it, there's no "wrong" value.
Consider a change from '0' to '1':

1. The first DFF in the chain goes meta-stable and as a result the 2nd DFF sees a '0' and outputs a '0'.
2. Chances are (see the word "dramatically") that by the 2nd cycle - the first flip flop has come into a stable determinable state and samples a '1'.
3. The 2nd DFF now sees a '1' and samples it correctly.

You didn't get an "error" in the pure sense of the word - just the correct output with a minor (single cycle) delay.

Thread closed as another thread by the same user was started on this topic in the ASIC section.
https://www.edaboard.com/showthread.php?t=367499