Stackup agreement between SW Tools and PCB Fabricator

Hello,
I'm just getting into analog RF design(L-band). I have done a lot of high speed digital stuff > 10Gb/s on differential pairs.

Typically we would call up the anticipated PCB manufacturer and get a stackup that they generated using their process and tools. For example 100 ohm differential space and trace numbers. We would then have the PCB layout team use these numbers.

In getting into the RF realm we've noticed a lot of VSWR across the band of our first board. Some of this was component pad size etc.

I realized we needed to develop with an EM solver. But since we get the stackup from the fabricator it doesn't agree with the stackups generated in the tools. I talked to their engineering dept. and there was what I felt a lot of hand waving. One thing that came out of it was they test using a TDR that only goes up to ~700MHz. I take that as my 950-2150MHz board isn't being verified at the correct frequencies. Is this correct?

The other thing was there doesn't seem to be a way to connect their process stackup numbers to the simulation tools. How does the industry use the simulation tools to design boards that are then fabricated as designed?


Thanks
Matt

Wrangler236 said:

Hello,
I'm just getting into analog RF design(L-band). I have done a lot of high speed digital stuff > 10Gb/s on differential pairs.

Typically we would call up the anticipated PCB manufacturer and get a stackup that they generated using their process and tools. For example 100 ohm differential space and trace numbers. We would then have the PCB layout team use these numbers.

In getting into the RF realm we've noticed a lot of VSWR across the band of our first board. Some of this was component pad size etc.

I realized we needed to develop with an EM solver. But since we get the stackup from the fabricator it doesn't agree with the stackups generated in the tools. I talked to their engineering dept. and there was what I felt a lot of hand waving. One thing that came out of it was they test using a TDR that only goes up to ~700MHz. I take that as my 950-2150MHz board isn't being verified at the correct frequencies. Is this correct?

The other thing was there doesn't seem to be a way to connect their process stackup numbers to the simulation tools. How does the industry use the simulation tools to design boards that are then fabricated as designed?


Thanks
Matt

Click to expand...

I'm pretty sure you can match the stackup numbers to the simulation tools. A simulator is supposed to do what you tell it do.

Wrangler236 said:

But since we get the stackup from the fabricator it doesn't agree with the stackups generated in the tools.

Click to expand...

Hi Matt,

maybe I misunderstand your comment, but of course you need to configure the EM tool stackup to match the actual hardware stackup (thicknesses and materials).

One known issue is FR4 dielectric, were the dielectric constant depends on the fibre/resin mixture. It can be 3.9 or 4.7, hardly specified at all. There are some "better" FR4-like materials with reasonable tolerances in dielectric constant, so that you can simulate with more confidence. True microwave PCB materials (e.g. Rogers substrates) are better for loss, are also specified with much tighter tolerances.

For coupled lines, there are some more details to consider in simulation to get the coupling between lines right, but that's mostly unrelated to the material/stackup topic.

Wrangler236 said:

One thing that came out of it was they test using a TDR that only goes up to ~700MHz. I take that as my 950-2150MHz board isn't being verified at the correct frequencies. Is this correct?

Click to expand...

Impedance of a straight coupled line segment does not change much from 700MHz to 2GHz. However, parasitics from wrong via impedance or open stubs can cause much more trouble at higher frequencies.

Best regards
Volker

Thanks for the responses. I think I need to add more detail...

When I design a stackup using Hyperlynx or Genesys I plug in the dielectric constant of the prepreg from the data sheet. To make a 50 ohm impedance I then adjust either the height from the GND plane or the width of the traces. In the past the PCB fabricator would then adjust the trace widths of the final design to get the right impedance per their process. In the digital world eg gigabit transceivers there are typically only the ac coupling caps and maybe an on board termination resistor. So there really aren't many opportunities for discontinuities. In the analog RF world I'm significantly more concerned with the pad size on lumped components since there are more of them. For example if the pad is larger than the trace there will be a discontinuity. So I don't want the PCB house changing the trace widths. As another example if I have to design a microstrip component such as a filter or coupler I don't want them changing its size to meet their impedance process variations and breaking the design.

Is there a typical process to design a microstrip component in software that will be manufactured without a per fabricator process change? Or do I just specify material dielectric and copper weight parameters and not specify finished impedance?

Wrangler236 said:

To make a 50 ohm impedance I then adjust either the height from the GND plane or the width of the traces. In the past the PCB fabricator would then adjust the trace widths of the final design to get the right impedance per their process.

Click to expand...

Somewhat different from what we RF guys do, with tightly controlled PCB materials, but I get your point. Sounds reasonable for high speed transmission lines.

Wrangler236 said:

Is there a typical process to design a microstrip component in software that will be manufactured without a per fabricator process change? Or do I just specify material dielectric and copper weight parameters and not specify finished impedance?

Click to expand...

Correct, no geometry tweaks for finished impedance, just build nominal dimesions. In RF designs, the PCB fabricators are not supposed to tweak the layout, so the materials must be known in advance. The designer specifies the substrate, i.e. Rogers RO4003 with thickness and copper details. For composite boards with digital + RF, there might be a tightly specified part stacked with some "slow" digital layers, separated by the RF ground plane, so that RF isn't influenced by tolerances in the digital stackup.

volker@muehlhaus said:

Somewhat different from what we RF guys do, with tightly controlled PCB materials, but I get your point. Sounds reasonable for high speed transmission lines.



Correct, no geometry tweaks for finished impedance, just build nominal dimesions. In RF designs, the PCB fabricators are not supposed to tweak the layout, so the materials must be known in advance. The designer specifies the substrate, i.e. Rogers RO4003 with thickness and copper details. For composite boards with digital + RF, there might be a tightly specified part stacked with some "slow" digital layers, separated by the RF ground plane, so that RF isn't influenced by tolerances in the digital stackup.

Click to expand...

This was the disconnect. Today they finally connected me with an RF focused sales guy at one of the shops. He said the same thing.

In general...
1. Don't specify impedance since they can't change any parameters.
2. Identify material that has tight tolerances. (He also mentioned Rogers for their rigorous specifications)
3. Specify all of the geometric parameters with tolerances.
4. Plan for some time to let them do a review of the board ahead of layout sign-off.

Thanks
Matt

The domain of controlled impedance manufacturing is mainly high speed digital design on high density PCB where production variation of trace widths affects impedances a lot. Substrate permittivity and thickness variation is an additional factor. Respectively etching parameters and trace widths are adjusted, either forehand based on process knowledge or after TDR measurement of test structures.