what should the verification plan be for a top level digital module?

what should the verification plan be for a top level digital module ?

what should the verification plan be for a top level digital module ? what should it have ? plz give me examples of corner cases

Re: what should the verification plan be for a top level digital module ?

At top level, you are mostly interested in connectivity checks and interaction between blocks.

Connectivity is somewhat easy. Interaction, not as much. You can't possibly verify all combinations of everything at the same time -- too many blocks. For real complex SoCs, there usually is at least one processor. Folks will then run software on this processor and assume that lays out the environment in a reasonable fashion, and this software usually matches the end final application. It gets very complex once we start talking about verifying power intent through functional simulation. You also have really high level metrics, for instance, a certain rendering has to be done at 60 frames per second. Your top level chip should be able to deliver that rendering even if the processor is getting interrupts from all over the place, and all the memory stack is not loaded with the ideal data, all caches are giving misses, this type of thing.

Real SoC verification is a nightmare because it transcends into product specification and goals.