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[SOLVED] Using range is slv case statement

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wtr

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Hello all,

I'm looking at some legacy code. The guy has done the following

Code VHDL - [expand]
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PADDR                                   : in  std_logic_vector(31 downto 0);
------------------------------------------------------------
signal PADDR_N                                  : natural range 0 to 1048575; -- 2^20 = [19:0]
------------------------------------------------------------
-- APB Bus    
    PADDR_N <= conv_integer(PADDR(19 downto 0));   
------------------------------------------------------------
if PSEL = '1' and PWRITE = '0' then                                          
                case PADDR_N is
 
                    -- MRI-0 (Base: 0x0000_0000)
                    when 16#00000# => PRDATA <= FPAD_SLV(32, ARM_WR_MRI0_DARK_START_S);
                    --- more options
                    when 16#B8000# to 16#B9FFC# => PRDATA <= ARM_RD_FDDR_RDATA;     -- 8KB Address Space


The use of a natural is used to allow the case statement to have a range.
I know slv ranges' wasn't allowed in the 93 vhdl.

nowadays could I do 
Code VHDL - [expand]
1

when x"B8000" to x"B9FFC" => PRDATA <= ARM_RD_FDDR_RDATA;     -- 8KB Address Space

Or do I need some fancy subtype range?

At this moment of time I haven't got access to a tool licenses check if this synthesis

Regards,
Wes
 

wesleytaylor said:
Hello all,

I'm looking at some legacy code. The guy has done the following

Code VHDL - [expand]
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PADDR                                   : in  std_logic_vector(31 downto 0);
------------------------------------------------------------
signal PADDR_N                                  : natural range 0 to 1048575; -- 2^20 = [19:0]
------------------------------------------------------------
-- APB Bus    
    PADDR_N <= conv_integer(PADDR(19 downto 0));   
------------------------------------------------------------
if PSEL = '1' and PWRITE = '0' then                                          
                case PADDR_N is
 
                    -- MRI-0 (Base: 0x0000_0000)
                    when 16#00000# => PRDATA <= FPAD_SLV(32, ARM_WR_MRI0_DARK_START_S);
                    --- more options
                    when 16#B8000# to 16#B9FFC# => PRDATA <= ARM_RD_FDDR_RDATA;     -- 8KB Address Space


The use of a natural is used to allow the case statement to have a range.
I know slv ranges' wasn't allowed in the 93 vhdl.

nowadays could I do 
Code VHDL - [expand]
1

when x"B8000" to x"B9FFC" => PRDATA <= ARM_RD_FDDR_RDATA;     -- 8KB Address Space

Or do I need some fancy subtype range?

At this moment of time I haven't got access to a tool licenses check if this synthesis

Regards,
Wes
Click to expand...

Nothing fancy possible - this just isnt possible with SLV for several reasons.
1. SLV are arrays, not discrete types like std_logic or integer.
2. Ranges only work for discrete types
3. A SLV is not a number anyway, just a bag'o'bits.

For this to work this way, you will have to convert it to a discrete type anyway.

BUT

What is included in VHDL 2008 is the matching case statement (case?), which allows the use of '-' in std_logic based arrays for case matching. One Caveat is you'll have to write it in binary. like this:

Code VHDL - [expand]
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case? addr_top_bits is
  when "1010_100-" => --"B8000" to "B9FFC"
  when "1010_101-" => --"BA000" to "BBFFC"
  .. etc


To be honest, Id stick with the '93 version.
 
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    wtr

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