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12 bit SAR ADC test result

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houjiali

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I have designed a 12 bit SAR ADC with CDAC. There are a 4-bit MSB section and a 8bit LSB section in the CDAC. The architecture of comparator is 3-stage pre-amplifier+latch,whose VCM is generated by a resistor ladder. The spec is 125sps(2Mhz CLK) .
I tested the chip with input of 1.1kHz and 1Mhz clk. The DNL in 1/4FS 1/2FS 3/4FS is quite high.
**broken link removed**
**broken link removed**
 

Do you want to ask a particular question? You also forget to tell what the first attachment exactly shows.
 

1.JPG2.JPG
The 1st attached pic is the FFT result. The 2nd one is DNL and INL

- - - Updated - - -

1.JPG2.JPG
The 1st attached pic is the FFT result. The 2nd one is DNL and INL
I dont know it's due to mismatch of the caps in the CADC or comparator or any other reasons?
 

Sorry to reply to my own post, but i want to add something more.

The carry from the LSB array to the MSB array (in your case B7 to B8 (considering LSB ==> B0 and MSB ==> B11) can conduct to large periodical (make sense) DNL due
to the mismatch of the attenuation capacitor (between your MSB and LSB ARRAY) and/or top/bottom plate parasitic capacitance.

Instead of having a ratio between 2 outputs Vout(0001 0000 0000) and Vout(0000 0000 0001) of 256:1 you have something like 257:1, and this ratio mismatch conducts to large DNL.


Read more:
"A 10.4-ENOB 120MS/s SAR ADC with DAC Linearity Calibration in 90 nm CMOS"
" Split Capacitor DAC Mismatch Calibration in Successive Approximation ADC"
"A 12b 50MS/s 2.1mW SAR ADC with Redundancy and Digital Background Calibration" (this one is an open access article from the MIT).

Hope it was clear, and i helped you.


PS: sorry for this english you just read, hope your eyes are not bleeding.
 
Thanks for your advise and reference paper.
I have checked the parasitic. The post_sim result is about 70dB, and no missing code in 2048 or 256. My process is TSMC180nm ELL.
I have done a lot of caculation and matlab modeling.
I find that if the MSB cap with an err of 1/512, the MSB-1 cap with an err of -1/(256), MSB-3 cap with an err of 1/256, MSB-4 with an err of 1/128. The INL result is similar to my testing result.

I dont know why the capacitors has mismatch like this. In this design, the route is wider than before, which lead to the cap unit cells has a bigger distances in the layout. Do you think the distance of the cap cells has some affect on the cap-match?
 

You can characterize capacitance mismatch (mis-weighting) using a field solver (in StarRC, QRC, or Calibre xRC) - you just need to specify a very high accuracy (0.01%) for the extraction (this feature is available in random walk field solvers only - i.e. StarRC, QRC, QuickCap,...).

I have done this many times, on many SAR ADC designs, you just need to wait long, as random walk algorithm converges quite slowly (1/sqrt(N)).

Max
 

Thank you Timeof, the time i want to answer to this, the thread was closed.



Sorry I didn t see your answer ..

Definitely the layout of the capacitors has to be done in a way to decrease parasitics capacitance on your bottom or top plate capacitor.

I m not sure about the relation between distance in the layout and the parasitics (intuitively i want to say yes it will decrease but as i can t prove it i prefer not be categoric).
What you can do is try to see if you have some tools like RVE from calibre, just the basic one, which gives you the amount of parasitics capacitances on each nets, and do some tests.

Try to check also "The Art of Analog Layout", Alan HASTINGS, it has a hole chapter about matching capacitors.

I hope you will find !


PS:If you can tell me the advancement, i will be thankful.
 

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