filip.amator
Full Member level 3
Hi All!
This is my first post on this forum
In my project, I want to overlay at the incoming video stream with a content stored in ROM memory (or dual-port RAM). The picture should be passed throught this piece of VHDL code to the another overlay unit or vga memory. The input data are encoded in very simple way: each 4 bit value at given address coresponds to one pixel. Although I got at the video monitor expected picture (background with an overlay in proper place) I see spourious pixels flashing within overlayed area. And now the question: Do you see and mistakes/errors in the code?
I made simulations in ModelSim but everything looks fine.
Project done in Quartus Prime Lite Edition, C5G board from Terasic with HDMI output.
This is my first post on this forum
In my project, I want to overlay at the incoming video stream with a content stored in ROM memory (or dual-port RAM). The picture should be passed throught this piece of VHDL code to the another overlay unit or vga memory. The input data are encoded in very simple way: each 4 bit value at given address coresponds to one pixel. Although I got at the video monitor expected picture (background with an overlay in proper place) I see spourious pixels flashing within overlayed area. And now the question: Do you see and mistakes/errors in the code?
I made simulations in ModelSim but everything looks fine.
Project done in Quartus Prime Lite Edition, C5G board from Terasic with HDMI output.
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; entity overlay is generic ( HRES : natural := 640; -- size of the screen VRES : natural := 480; SIZE_X : natural := 100; -- coordiantes of top left corner of overlay SIZE_Y : natural := 100; OVER_POS_X : natural := 100; -- size of the overlay OVER_POS_Y : natural := 100 ); port ( i_clk : in std_logic; -- pixel clock i_clk_en : in std_logic; i_reset_n : in std_logic; i_addr : in std_logic_vector(18 downto 0); -- pixer address: address 0 coresponds to column 0, row 0; address 307199 to column 639, row 479 i_data : in std_logic_vector(3 downto 0); -- 4 bits per pixel, 16 colours o_addr : out std_logic_vector(18 downto 0); -- output stream passed to another overlay unit or video memory o_data : out std_logic_vector(3 downto 0) ); end overlay; architecture behavioral of overlay is -- rom memory with stored 100x100 bitmap to be placed on the top of incoming picure. COMPONENT over1 IS PORT ( address : IN STD_LOGIC_VECTOR (13 DOWNTO 0); clock : IN STD_LOGIC := '1'; q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) ); END COMPONENT over1; signal s_addr : std_logic_vector(18 DOWNTO 0); signal s_data : std_logic_vector(3 DOWNTO 0); signal s_posx : integer range 0 to HRES-1 := 0; -- pixel coordinates signal s_posy : integer range 0 to VRES-1 := 0; -- pixel coordinates signal s_overaddr : STD_LOGIC_VECTOR (13 DOWNTO 0); -- address of the pixel to be repleaced signal s_overdata : std_logic_vector(3 DOWNTO 0); begin -- no flipflops at the output of the ROM over1ram : over1 port map ( address => s_overaddr, clock => i_clk, q => s_overdata ); s_posx <= to_integer(unsigned(i_addr) mod HRES); s_posy <= to_integer((unsigned(i_addr) - (unsigned(i_addr) mod HRES))/HRES); -- outside of overlay area this value might be incorrect. s_overaddr <= std_logic_vector(to_unsigned(s_posx - OVER_POS_X + SIZE_X*(s_posy - OVER_POS_Y),s_overaddr'length)); process (i_clk,i_reset_n) begin if (i_reset_n='0') then null; else if (i_clk='1' and i_clk'event and i_clk_en='1') then for i in 0 to 1 loop case i is when 0 => if ((s_posx > OVER_POS_X-1) and (s_posx < OVER_POS_X+SIZE_X) and (s_posy > OVER_POS_Y-1) and (s_posy < OVER_POS_Y+SIZE_Y)) then null; else null; end if; s_data <= i_data; s_addr <= i_addr; when 1 => null; if ((s_posx > OVER_POS_X) and (s_posx < OVER_POS_X+SIZE_X+1) and (s_posy > OVER_POS_Y-1) and (s_posy < OVER_POS_Y+SIZE_Y)) then -- o_data <= s_data when s_overdata="0000" else s_overdata; if(s_overdata="0000") then o_data <= s_data; else o_data <= s_overdata; end if; o_addr <= s_addr; else o_data <= s_data; o_addr <= s_addr; end if; when others => null; end case; end loop; end if; end if; end process; end architecture;