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Simulation of latch with concurrent statements

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mahmood.n

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I wrote a T latch with concurrent statements in VHDL

Code:
entity tlatch is
	port( t, e: in bit;
	q, qb: inout bit);
end;
architecture x of tlatch is
	signal o1, o2: bit;
begin
	o1 <= t and e and q;
	o2 <= t and e and qb;
	q <= o1 nor qb;
	qb <= q nor o2;
end;

As I simulate this code with active-hdl, I get this error

Code:
# KERNEL: Stopped at time 0 ps + 10000.
# KERNEL: Error: KERNEL_0160 Delta count overflow. Increase the iteration limit using -i argument for asim or the matching entry in simulation preferences.
I increased the value from 5000 to 10000 but still get the same error.
Any idea?
 

I have seen them same "T latch" and also a "JK latch" in internet publications and even in a book. According to my understanding of digital logic, it can't be implemented. You can make a physically plausible gate simulation by adding transport delay to each of the four gates and see what happens. I expect a kind of gated ring oscillator.

A T-FF can be modeled as purely combinational circuit around a master slave FF or a similar circuit with edge edge sensitive behavior.
 
I wrote a T latch with concurrent statements in VHDL

Code:
entity tlatch is
	port( t, e: in bit;
	q, qb: inout bit);
end;
architecture x of tlatch is
	signal o1, o2: bit;
begin
	o1 <= t and e and q;
	o2 <= t and e and qb;
	q <= o1 nor qb;
	qb <= q nor o2;
end;

As I simulate this code with active-hdl, I get this error

Code:
# KERNEL: Stopped at time 0 ps + 10000.
# KERNEL: Error: KERNEL_0160 Delta count overflow. Increase the iteration limit using -i argument for asim or the matching entry in simulation preferences.
I increased the value from 5000 to 10000 but still get the same error.
Any idea?

I can assure you that even the best simulators out there will choke when seeing this type of logic. I don't want to go into details of update cycles, deltas, etc, but essentially this logic puts the simulator in a loop. Increasing the iteration limit will not help.
 
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