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Does gate need on the top and bottom of Mos, to get symmetry?

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diego.fan

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I'm drawing common centroid layout of current mirror. I'm new to analog layout. On the left and right side of the 1st and the last column of Mos, I think I should put dummy.

Do I also need put dummy on the top and bottom of the top and bottom row of Mos?
(If source and drain is on the left and right side of Mos)

In cadence, edit Instance Properties, I can choose "Gate M1 contacts" : both. Which will make two gates above and below a single Mos. Do I need to put two gate in one Mos to increase symmetry?

Thanks a lot!
 

Contacts at both ends would improve symmetry vs contacts
at one end, but alternating ends. It will also "push away"
local litho mismatch actors (if no contact over active, then
next active must be further away, etc.). But another
gate contact is not the same as a "dummy" row of FETs
(not necessarily full sized, you just want to equalize the
close-in field loading etc. as seen from the FEt-bank,
looking out in all directions).

Double gate contacts does reduce gate resistance and
for high frequency stuff this is always good.
 

Thanks, dick_freebird! Could you please explain "if no contact over active, then next active must be further away, etc."

Another question:
not necessarily full sized, you just want to equalize the close-in field loading.
For example, if the FET is width 3um, length 2um. 0.35um technology.
Can I use 3um width, 0.35um length FET to do the dummy. Someone told me that I should use the same size 3um, 2um. Or at least width 3um, length 1um. But I don't know why.
 

If poly gate contact is allowed over active then active-
active min spacing might set the distance between "bars".

If contact must be outside active then spacing would be
probably poly-poly defined, with active-active spacing
being poly-poly+2*contact-active.

At some point (which you may be unable to determine)
a given active to active real (as opposed to rule) spacing
looks "enough like" open field, as far as litho loading
effects go. And this is what dummies are meant to address.

Dummies could be less W than the "real deal" FETs. How
much is enough, again may not be known. Maybe a couple
contacts' worth of width, something above min but less
than the "real deal" FET W might be a good tradeoff. Of
course you could go full replica if you were not in an area
sensitive situation. But who gets that luxury other than
test chip designers, or folks working on I/O-limited SSI
stuff?
 

dick_freebird said:
If poly gate contact is allowed over active then active-
active min spacing might set the distance between "bars".

If contact must be outside active then spacing would be
probably poly-poly defined, with active-active spacing
being poly-poly+2*contact-active.

At some point (which you may be unable to determine)
a given active to active real (as opposed to rule) spacing
looks "enough like" open field, as far as litho loading
effects go. And this is what dummies are meant to address.

Dummies could be less W than the "real deal" FETs. How
much is enough, again may not be known. Maybe a couple
contacts' worth of width, something above min but less
than the "real deal" FET W might be a good tradeoff. Of
course you could go full replica if you were not in an area
sensitive situation. But who gets that luxury other than
test chip designers, or folks working on I/O-limited SSI
stuff?
Click to expand...


Hi, I saw your another reply in https://www.edaboard.com/threads/347241/
RF CMOS designers almost always contact both ends
of the gate.

In cadence there are two ways in "Gate M1 contacts": both and Strapped.
From the aspect of connection, I should choose strapped. Because I can only use one line to connect one of two gates and strapped way can connect two gates on the transistor. Is there some drawback in "Strapped"?

Because if there is no drawback, why should I choose "both"? Using both, I must use two separated line to connect two gates of one transistor? I think I will always choose "Strapped".

Thanks!
 

"Strapped" probably auto-draws the gate ends connection
on Met1 for you. Which then probably pushes on the S/D
metallization, making FET larger with marginally more Rs, Rd.
Also may (depending) add more fringing Cgd, Cgs than (say)
via-pillars up to a higher metal layer.

You'd probably have to play with a 3D EM simulator to see
the differences, and see whether the models comprehend
this low level device construction detail (properly) or not.

This is not about Cadence per se, it's the foundry's choice
to develop the PCells with this option.
 

dick_freebird said:
"Strapped" probably auto-draws the gate ends connection
on Met1 for you. Which then probably pushes on the S/D
metallization, making FET larger with marginally more Rs, Rd.
Also may (depending) add more fringing Cgd, Cgs than (say)
via-pillars up to a higher metal layer.

You'd probably have to play with a 3D EM simulator to see
the differences, and see whether the models comprehend
this low level device construction detail (properly) or not.

This is not about Cadence per se, it's the foundry's choice
to develop the PCells with this option.
Click to expand...


Screenshot from 2017-05-03 10-51-29.png

Yes, you are right. The left hand is strapped. the right hand is both. Same size, the only difference is in strapped, there is metal connecting both gates.
Because my design works in lower than 100kHz. Compared to EM simulation, I do hope to know if there is some matching difference between these two ways.

I think i prefer to choose "strapped". Because it don't need draw two separated line to connect two gates, if there is no mismatch problem.
 

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