Can I make Mos transistor's width shorter than its length?

I am designing an column of current mirror. To achieve good matching, I decrease W/L to increase Vgs-Vt. Now my W/L is 3/8. Width is shorter than length.
Is it acceptable?

Someone said it will cause the Mos model inaccurate. Do you have some idea about it? I also search in this forum, and see someone said it's ok. I tried to google it, but don't find something valuable.

What's your experience? Thanks!!

It's been the norm for a long time in larger-feature analog
MOS design. Whether the model covers the geometry is
dependent on what the foundry thinks it needs to support.
For mixed signal, almost certainly the L>W case will be
covered (and PDK docs should tell you the limits of accurate
geometry modeling explicitly). For "plain digital" you may not
see much emphasis, and maybe sloppy modeling, for long
devices as these would have no use in core logic or high
speed I/Os (or, would be considered "non-critical").

Since W/L ratio increases ( not exaggerated ), the matching also increases.
Larger area is principally controlled better in term of matching ( it's also valid for BJTs ).If you intend to decrease Vt, you can tie "Bulk" node of NMOS to lower potential than Source.( This is higher potential for PMOS ).There are other compromises too but if the first priority is matching, larger are is better.
Simulation models are less accurate for small sized semiconductor components.It's true what you heard..

Thanks, Bigboss!

BigBoss said:

Since W/L ratio increases ( not exaggerated ), the matching also increases.

Click to expand...

Does it means W/L or W*L? Because if it is W/L, I can make small L and large W, which can have a good matching. If it's W*L, I can also make large L to increase matching. Someone told me that I can make large L to increase matching. It makes me puzzled.

BigBoss said:

Simulation models are less accurate for small sized semiconductor components.

Click to expand...

I don't mean small size. I mean if L>W(both are not the minimum size), is simulation models are less accurate?

By the way, If L and W is too large, for example 0.35um technology, L=3um, W= is 50u, will the simulation models be less accurate?

It need much practical experience which I really lack of. Thanks!

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Thanks,dick_freebird. May I ask where I can find PDK. Now I have many docs from foundry such as Design rules, layout rules manual, electrical parametes,ESD and latch-up guidlines. But I don't know which one is PDK?

And if I search in PDK, what's key word I should choose?

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dick_freebird said:

It's been the norm for a long time in larger-feature analog
MOS design. Whether the model covers the geometry is
dependent on what the foundry thinks it needs to support.
For mixed signal, almost certainly the L>W case will be
covered (and PDK docs should tell you the limits of accurate
geometry modeling explicitly). For "plain digital" you may not
see much emphasis, and maybe sloppy modeling, for long
devices as these would have no use in core logic or high
speed I/Os (or, would be considered "non-critical").

Click to expand...

Thanks,dick_freebird. May I ask where I can find PDK. Now I have many docs from foundry such as Design rules, layout rules manual, electrical parametes,ESD and latch-up guidlines. But I don't know which one is PDK?

And if I search in PDK, what's key word I should choose?

PDK is the sum of the foundry CAD data (models, rules,
symbols, PCells) and documentation (modeling and
groundrules documents, application notes, device
descriptions and so on). Often provided as a single
zip / .tgz file, but sometimes hosted piecemeal on
the foundry's e-biz portal (there you need a login and
their approval).

I believe the modeling documents would be the place
to find answers to the original question about model
fidelity vs geometry specifics.