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How to store incoming data for later usage on a spartan6 device

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moro

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Hello,

i am "fighting" with a design where 2 32bit counters are generating data at diferent speeds.


The counters are enabled by a 1second gate signal, and on the falling edge of the signal, just when it reached 1s, i store the current counters values in a register for later usage (to be send on a uart module).

Each counter produces a 32bit value, in the end i have a 64bit value containing the two counters result, where i also add another 8bits containing a end header 8'h 0A.

So in total i have 72 bits



I have attached a simulation , where the red signal is the trigger and the blue one is the 64bit register
counter.png

The code for this is bellow



Code:
module mux_64bit( trigger, data72_in, data72_hold,rdy);
    input trigger;
    input [71:0] data72_in;
    output reg [71:0] data72_hold = 0;
    output reg rdy=0;
	 
    reg [71:0] buffer =0;
   
	
	
always@(negedge trigger) begin
      
        if(!trigger) begin
	           buffer<=data72_in;	 
		   data72_hold <= buffer;  
		   rdy <=1'b1;  // flag for "data ready"
       end
       else begin
		  	buffer<=72'b0;
			rdy <= 1'b0;
      end
  end

endmodule



And the top module instantiation

Code:
mux_72bit  muxy(
    .trigger(enable),// 1 second "store" signal
    .data72_in({r32,s32,8'h0A}), // concatenate 2x32bits , plus a end header 0A 
    .data72_hold(data72),//output to a output reg of main module
    .rdy(ready) // ready signal for uart module

    );


So in simulation of course everything is working as expected, but when implemented on hardware... i have some random values inside the 64bit range, the 0A header is ok.

My question is, whats the practical aproach for such a procedure? Or how to safely store the data to be available between each cycle?

Thanks
 

Yeah, you're using an asynchronous trigger signal, no clock and you expect this to work on hardware? You probably don't even have the constraints entered in the UCF, XDC, or SDC file to ensure it works.

Use a system clock of some sort and generate the trigger as a clock enable to load the register. It will likely be much easier to design and will also be more likely to work.
 

Hello ads-ee,

i am a bit confused, the picture i shown above was a bit simplificated... On the chip i have 2 clock sources,

- 1st is a "sys clock" which is driving the counter1 ( reference counter), and also drives timing for a 1 second gate signal generator

- 2nd clock source (unknown period/freq) drives counter2

The 2nd clock also provides signal clock for a flipflop where D(data) is tied to the 1s gate signal, the Q output of the flipflop generates the trigger signal for both counters and the 72bit mux.

Here is my main timing where
fclk - unknown clock signal source
clk - system clock
sec - 1second gate signal
cnt_enable - is the trigger signal


counter2.PNG


In the UCF file for the clock pins i have defined the following, are these enough?

Code:
NET "clk" LOC="N8" | IOSTANDARD=LVCMOS33 ;   
NET "clk" TNM_NET = clk;
TIMESPEC TS_clk = PERIOD "clk" 20 ns HIGH 50%;

NET "fclk"   LOC="H13" | IOSTANDARD=LVCMOS12  ; 
NET "fclk" TNM_NET = "fclk";
TIMESPEC TS_fclk = PERIOD "fclk" 20 ns HIGH 50 %;




Use a system clock of some sort and generate the trigger as a clock enable to load the register

Something like this?
Code:
input RST, clock;
input [71:0] D;
output reg [71:0] Q=0;
output reg rdy=0;

always@(posedge clock) begin
      
        if(!RST) begin
	           Q<=D;	 
		    rdy <=1'b1; 
       end
       else begin
		  	Q<=0;
			rdy <= 1'b0;
      end
  end

endmodule
 

In the UCF file for the clock pins i have defined the following, are these enough?

Code:
NET "clk" LOC="N8" | IOSTANDARD=LVCMOS33 ;   
NET "clk" TNM_NET = clk;
TIMESPEC TS_clk = PERIOD "clk" 20 ns HIGH 50%;

NET "fclk"   LOC="H13" | IOSTANDARD=LVCMOS12  ; 
NET "fclk" TNM_NET = "fclk";
TIMESPEC TS_fclk = PERIOD "fclk" 20 ns HIGH 50 %;
No it's not enough, because trigger is a clock:
Code:
always@(negedge trigger) begin
      
        if(!trigger) begin
	           buffer<=data72_in;	 
		   data72_hold <= buffer;  
		   rdy <=1'b1;  // flag for "data ready"
       end
       else begin
		  	buffer<=72'b0;
			rdy <= 1'b0;
      end
  end
and you would require a create generated clock constraint in your ucf. This is a really bad way to design in FPGAs.

And based on your description you've got multiple feedback paths that are all CDCs, and you aren't using any resynchronizers, well that isn't going to work. Use proper CDC techniques and don't create clocks in your logic (using posedge/negedge with non-clock signals).
 

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