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[SOLVED] How to replace transistor with Verilog-A model in Eldo?

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vaah

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Hello guys,

I want to replace the extracted transistors with a Verilog-A model in Eldo. I know ".Bind" command provides some options to do it. But the thing is that I am not sure how this command works for the extracted netlist!
I would greatly appreciate it if you could help me out with this.

Here is the netlist
_______________________________________________
.subckt AYKL VSS R[1] VDD L[1]
mXAYK_1/KSL VDD R[1] L[1] VSSI nch L=1.0e-06 W=6.0e-06
mXAYK_2/KSL VDD R[1] L[1] VSSI nch L=1.0e-06 W=6.0e-06
.ends
____________________________________________________

THANKS IN ADVANCE.
 

In case someone has the same issue

".BIND" command and subcircuit should be in one "cir" file not separated. From manual, you may get that you need another ".cir" file to do the substitution! But it's not the case!
 

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