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[SOLVED] Question of report_timing command in PrimeTime

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hungtaowu

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In PrimeTime® Fundamentals User Guide Version D-2010.06, June 2010, P6-3, a report_timing result is shown below:

Code:
[I]
pt_shell> report_timing
****************************************
Report : timing
Design : FP_SHR
****************************************
Operating Conditions:
Wire Loading Model Mode: top
Startpoint: a (input port)
Endpoint: c_d (output port)
Path Group: default
Path Type: max
Point Incr Path
----------------------------------------------------
input external delay 10.00 10.00 r
a (in) 0.00 10.00 r
m1/Z (MUX21H) 1.00 11.00 r
u1/S (FA1) 1.00 12.00 r
c_d/Z (AN2) 1.00 13.00 r
c_d (out) 0.00 13.00 r
data arrival time 13.00

max_delay 15.00 15.00
output external delay -10.00 5.00
data required time 5.00
----------------------------------------------------
data required time 5.00
data arrival time -13.00
----------------------------------------------------
slack (VIOLATED) -8.00[/I]

My question is about data required time. Does the max_delay in the data required time calculation includes input external delay + internal combinational delay + output external delay?


But I also get the maximum delay constraint in website: https://tech.tdzire.com/when-to-use-maximum-delay-constraint-for-synthesistiming-analysis/, which is shown below:

MAX-DELAY-e1360943183880.jpg

The data required time and data arrival time here is calculated as below:

The slack calculation for setup check of Primetime is as below in this scenario
Data Arrival Time (DAT) = input external delay + IN1 – OUT1 actual delay
Data required Time (DRT) = one clock cycle – clock uncertainty – output external delay +
max_delay requirement value
setup slack = DRT – DAT


It seems that the Data required Time calculated here is not consistent with that in the ptugf report_timing example. So is there anything wrong?
 

Does the max_delay in the data required time calculation includes input external delay + internal combinational delay + output external delay?
-----

Yes, from the report above, we can see that input delay was taken into the arrival time while path delay + output delay were taken into required time.
 
Hi slutarius:
3ks for you reply. I don't understand why one clock cycle is added in the Data required Time (DRT) calculation in the second example:
Data required Time (DRT) = one clock cycle – clock uncertainty – output external delay + max_delay requirement value
which is different from the first example.
 

Because there are clock that associated with input delay and output delay constraint for IN and OUT ports.
And below are the description of set_max_delay command:

"Individual maximum delay targets are automatically derived from clock waveforms and port input or output delays. For more information, see the create_clock, set_input_delay, and set_output_delay man pages."

You can use man command for more details.
 

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