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Design for testability - time limits in practice

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andrew_ww

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Hi!

I would like to ask about optimized DFT in practice. In nuthsell, how much time it is supposed to consume to test a new ASIC ? (After it is manufactured, and shipped from the fab.)

If i want less time to test, i should build in more complex self-tests, use more silicon. With zero amount of silicon, still i can test the device by all of its functionality. That just takes more time (much more in this case, it will be a highly integrated logical device with memory and many state machines inside). How should i balance it? For example, i can guess, that a new device may demand 10 milliseconds in the tester, it is okay. What about 1 second? 5 seconds? 10? 200? Where i should think, that time is too much already?
 

this is mostly a management decision because it is a cost decision. it depends heavily on the volume, ie, how many dies you are getting.
 

Let we assume, it is high volume (continuous pressure on both: more cheap die and more test speed).
 

Test cost is an element of production cost and eventual
profit. Similar to yield, and both also give some probability
of "escapes" whose eventual impact can't be so well
quantified or even bounded (corporate black eye, like).
So you will see people who don't have the problem of
being responsible for cost or schedule dictating that
no amount of effort is too much.

Do the math on test time. A million units at a minute
a pop, is going to blow your delivery schedule probably.
Or you get to rent the entire test house for a few
weeks.
 
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