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Current source in CML: lvt or normal??

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NovelPanda

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Dear All:

I have many CML topologies in my design. The differential pairs are all lvt RF transistor. I want to know what transistor should I use to form the current source, lvt_nmos (Vth=410mV) or normal nmos (Vth=490mV)? I prefer lvt but what is the potential consequences?

Thanks in advance~
 

I think Normal MOS Vt value is less sensitive to process variations, so this should be chosen.
 

With so little difference in VT (nominal) I don't think it
matters a whole lot. Either one is big enough that you
can throttle back several decades of current before
Vgs=0, so mirrors ought to be reliable-ish in matching.
A question is, does your CML perform any better (like
max well formed frequency vs current per gate) with
a current-source or a resistive tail characteristic?
The normal MOS will be less driven into saturation
at your setpoint current (or, will have to be wider).
If you need to run at a very low headroom then
lvt picks you up some tens of mV before you roll
over into linear region on the sources (sinks). The
question of which is better, remains.
 

Thanks Bigboss and freebird. Actually I consider lvt as current source because I really concern about its headroom, and the Vds is about 210mV (~65mV higher than Vdsat=145mV) in the conventional master-slave DFF under 1.1V supply.Choose bigger size of differential pair could help but it increases parasitics that stresses previous stage which is not desired in high speed.
 

Use lvt! It will be easier in the layout. You can put them closer to each other.
 

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