arve9066
Member level 2
Code:
entity wb_sl_adc is
generic
(
NR_OF_DBGPORTS : positive := 1
);
Port ( syscon_i : in rec_syscon_port;
master_i : in rec_master_port;
adcclock_80Mhz : in STD_LOGIC;
data1 : in std_logic_vector(13 downto 0);
data2 : in std_logic_vector(13 downto 0);
of1 : in std_logic;
of2 : in std_logic;
calib1 : out std_logic;
calib2 : out std_logic;
uart_txd: out std_logic;
uart_rxd: in std_logic;
--uart_rts: in std_logic;
--uart_cts: in std_logic;
spi_sck: out std_logic;
spi_ss: out std_logic;
spi_mosi: out std_logic;
spi_miso: in std_logic;
j: buffer integer range 0 to 10;
debug : out std_logic_vector((NR_OF_DBGPORTS-1) downto 0);
slave_o : out rec_slave_port);
end wb_sl_adc;
inst_wb_sl_adc : wb_sl_adc
generic map (
NR_OF_DBGPORTS => 1)
port map(
syscon_i => syscon,
slave_o => intercon.slaves.slave(SL_ADC_ID-1),
master_i => intercon.slaves.master(SL_ADC_ID-1),
adcclock_80Mhz => adcfix_clock80_i,
data1 => pin_adc_d1_i,
data2 => pin_adc_d2_i,
of1 => pin_adc_of1_i,
of2 => pin_adc_of2_i,
uart_txd => pin_uart_tx_o,
uart_rxd => pin_uart_rx_i,
calib1 => pin_cal1_o,
calib2 => pin_cal2_o,
--uart_rts => pin_uart_rts_i,
--uart_cts => pin_uart_cts_i,
spi_sck => spi_clk_sig,
spi_ss => pin_spi_ss_o,
spi_mosi => pin_spi_mosi_o,
spi_miso => pin_spi_miso_i,
debug => open
);I get these errors while I compile my project
"Formal port/generic <calib1> is not declared in <wb_sl_adc>"
"Formal <spi_miso> has no actual or default value"
I have the following defined in the entity of the top level vhdl file as well.
[/CODE] pin_cal1_o : out std_logic; -- Calibration Signal 1
pin_cal2_o : out std_logic; -- Calibration Signal 2 [/CODE]
I had no errors before I added the calib1 and calib2 to the entity, but after that I get the above errors. Somehow I feel I am doing something really basic wrong. But cannot seem to identify it.