Preserving net naming in Synthesis using DC

I'm tring to preserve a list of ports of a specific module in the hierarcy that I'm synthesising with Synopsys DC. This is required because I'm runing some simulations at the gate level and in the test-bench I'm using those signals.

Before synthesis I run set_dont_touch on the nets I'm interested in so it will be preserved their name and not optimized:
Then I run the the report command just to make sure that I have got the right ports naming and took it from the right path:
This reports correctly all the nets I'm interested in and suggests that the attribute worked.

This works almost all the time. However there are cases (some minimal random changes in the RTL at different levels or no changes at all) when the one of multiple nets are not preserved. For example I have a 32 bit data bus called Data and is split in different 32 wires named as Data_1_, Data_2_, Data_3_, ...etc and only few seemd to be inverted with the name Data_18_BAR, Data_19_BAR. This makes the simulation at the gate level to fail because it can't find anymore the bus Data or some of those ports are inverted and is not matching what was expecting.

How can I make sure those ports are preserved and not optimized during synthesis? I'm only interested in a few ports, for the rest I don't care and can be optimized as it likes. The ports are not in the top level, 2 modules down of the hierarcy.

Do you have the code and the synthesis scripts? Does the circuit work if you modify the test bench this way:

assign Data[0] = Data_1_;
assign Data[1] = Data_2_;
etc

Click to expand...

Confirm the circuit works with this change. If this doesn't work, then you have a bigger problem.

The answer is yes for both questions. I have the all the code and synthesis scripts. Also the sims works if I change the names in the test bench to mach the netlist new signals. The problem is next time when there are some more RTL updates, the tool might decide to optimize in a different way and I don't want to constantly modify the testbench. I just want to keep those ports as they are.

I made some experiments by setting set_boundary_optimization attribute to false for the module I'm interested and it seemed to worked. Not sure yet if this will give me constant results and if is affecting in any way the QoR of the synthesis.

birbal said:

The answer is yes for both questions. I have the all the code and synthesis scripts. Also the sims works if I change the names in the test bench to mach the netlist new signals. The problem is next time when there are some more RTL updates, the tool might decide to optimize in a different way and I don't want to constantly modify the testbench. I just want to keep those ports as they are.

I made some experiments by setting set_boundary_optimization attribute to false for the module I'm interested and it seemed to worked. Not sure yet if this will give me constant results and if is affecting in any way the QoR of the synthesis.

Click to expand...

Usually, yes, QoR will be affected. You could also try pragmas embedded directly to your code.