Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Correct BUMP Pitch to use

Status
Not open for further replies.

GDesign

Newbie level 5
Joined
Apr 7, 2017
Messages
9
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
63
Hi,
I am working on TSMC 40nm.
I need to use BUMP cells and I would like to get the right bump pitch to use.
Inside the BUMP's documentation I read the following differences that determine the "Bump pitch":

"On Silicon Dimension" and "Design Dimension"

What Are these difference ?

Thanks
 

BUMP pitch: you have to contact the foundry. Multiple pitches are possible, multiple bump sizes are possible. If you are in an MPW, this was probably already picked for you and cannot be changed.

The difference is that silicon is sometimes shrunk when compared to design units. You draw 100nm, but with a 95% shrink, it will become 95nm on the real chip. This is really common when technologies become mature.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top