# Generate 40 Hz from 44MHz clock

1. ## Generate 40 Hz from 44MHz clock

I am designing FPGA using VHDL. Please suggest a logic to generate exactly 40 Hz from 44MHz using FPGA alone.

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2. ## Re: Generate 40 Hz from 44MHz clock

Hi,

44MHz ÷ 40Hz = 1 100 000
--> you need 1 100 000 pulses of 44MHz for one 40Hz pulse
Each pulse has two edges: thus 550 000 pulses of 44MHz from one 40Hz edge to the next.

Now use a 20 bit binary counter running from 44MHz.
Compare it with 549 999 (count from 0 to 549 999)
On compare match: toggle the 40Hz signal and synchronously reset the 20 bit counter.

Klaus

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3. ## Re: Generate 40 Hz from 44MHz clock

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What he said.

Just remember things are in multiples of two.

Therefore in order to make 1100000 you need to know what the x is in 2^x.

On a side note, since I assume you're new to vhdl

```Code VHDL - [expand]1
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signal s : unsigned(x-1 downto 0);
s <= s+1;
signal slv : std_logic_vector(x-1 downto 0);
-- requires type conversion
slv <= std_logic_vector(unsigned(slv)+ 1);

[/syntax]

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4. ## Re: Generate 40 Hz from 44MHz clock

Originally Posted by wesleytaylor
```Code VHDL - [expand]1