# using if statement in verilog

1. ## using if statement in verilog

I am getting a 50bit signed number result from my multiplier. Now based on the sign bit my output would be classified either o or 1. I have written the verilog code as such but I am receiving such error. Could anyone guide me?

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2. ## Re: using if statement in verilog

You want to put this into an always block, or just have an assignment with a ternary operator, or just assign class to the bit at index 49.

This is attempting to use the if-generate structure, which conditionally includes logic at synthesis time based on constant values. I didn't realize you could skip "generate" but Verilog is fairly relaxed on syntax rules.

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3. ## Re: using if statement in verilog

could you correct me the code that i have made error in the screenshot ?

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4. ## Re: using if statement in verilog

Look like your are writing Verilog with a software coding style. Check again how to write verilog if/else construct.

With that logic, you can imagine a wire which use to connect svm[49] to class directly.
It can be archieve by simple assignment.

5. ## Re: using if statement in verilog

Why are you make it overcomplicated? Why not:

assign class = svm[49];

6. ## Re: using if statement in verilog

When svm[49] is HIGH, then class has value 1b'1, else it has value 1b'0. As you have defined no sensitivity list so I would write it as...
assign class = (svm[49]) ? 1b'1 : 1b'0;

7. ## Re: using if statement in verilog

Originally Posted by dpaul
assign class = (svm[49]) ? 1b'1 : 1b'0;
There is no point of checking the bit 49, class can be assigned to its value straight away. As simple as:
assign class = svm[49];

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8. ## Re: using if statement in verilog

else
If you want to learn then know this

assign
Continuous assignments are the most basic assignment in dataflow modelling. Continuous assignments are used to model in combinational logic. It drives values into the nets.

In vhdl think of this as
```Code VHDL - [expand]1
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-- a mux/switch
x <= a when b else c;
-- constant assign
y <= consant```

Whereas in Verilog
```Code Verilog - [expand]1
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// mux or switch
assign x = b ? a : c;
// constant assignment
assign y = somevalue;```

What you implemented was a sequential if, with combinatorial assign. In that method you'd need a
```Code Verilog - [expand]1
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always @ *
begin
if b==1 x = a; else x=c; //Verilog uses begin and end as c language { }
end```

VGoodtimes said as much, but he's such an expert that he uses expert speak - like ternary (?:) operations

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