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    using if statement in verilog

    I am getting a 50bit signed number result from my multiplier. Now based on the sign bit my output would be classified either o or 1. I have written the verilog code as such Click image for larger version. 

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ID:	138072 but I am receiving such error. Could anyone guide me?

    •   Alt21st April 2017, 05:22

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    Re: using if statement in verilog

    You want to put this into an always block, or just have an assignment with a ternary operator, or just assign class to the bit at index 49.

    This is attempting to use the if-generate structure, which conditionally includes logic at synthesis time based on constant values. I didn't realize you could skip "generate" but Verilog is fairly relaxed on syntax rules.


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    •   Alt21st April 2017, 05:36

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    Re: using if statement in verilog

    could you correct me the code that i have made error in the screenshot ?



    •   Alt21st April 2017, 06:57

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    Re: using if statement in verilog

    Look like your are writing Verilog with a software coding style. Check again how to write verilog if/else construct.

    With that logic, you can imagine a wire which use to connect svm[49] to class directly.
    It can be archieve by simple assignment.
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    Re: using if statement in verilog

    Why are you make it overcomplicated? Why not:

    assign class = svm[49];



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    Re: using if statement in verilog

    When svm[49] is HIGH, then class has value 1b'1, else it has value 1b'0. As you have defined no sensitivity list so I would write it as...
    assign class = (svm[49]) ? 1b'1 : 1b'0;
    Sharing my ideas and knowledge + learning from the experiences of others is what I am looking for.
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    Re: using if statement in verilog

    Quote Originally Posted by dpaul View Post
    assign class = (svm[49]) ? 1b'1 : 1b'0;
    There is no point of checking the bit 49, class can be assigned to its value straight away. As simple as:
    assign class = svm[49];



    •   Alt21st April 2017, 14:43

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    Re: using if statement in verilog

    If you don't want to learn then birbal has your answer,
    else
    If you want to learn then know this

    assign
    Continuous assignments are the most basic assignment in dataflow modelling. Continuous assignments are used to model in combinational logic. It drives values into the nets.

    In vhdl think of this as
    Code VHDL - [expand]
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    -- a mux/switch
    x <= a when b else c;
    -- constant assign
    y <= consant

    Whereas in Verilog
    Code Verilog - [expand]
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    // mux or switch
    assign x = b ? a : c;
    // constant assignment
    assign y = somevalue;

    What you implemented was a sequential if, with combinatorial assign. In that method you'd need a
    Code Verilog - [expand]
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    always @ *
    begin
      if b==1 x = a; else x=c; //Verilog uses begin and end as c language { }
    end

    VGoodtimes said as much, but he's such an expert that he uses expert speak - like ternary (?:) operations



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