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Enabling Code coverage in VCS

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koolklara

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Hello,

I have been trying to enable code coverage in VCS and running into some issues.

I added "-cm line" switch to my compile and simulation and

" -metric line" to the command used to extract the line coverage information from the vdb.

The command I use is,

urg -metric line -dir <path_dir> -dbname <path_to_vdb>

The problem is, I only see coverage getting enabled at the leaf nodes. I also have verilog code sometimes at the parent level.

For e.g.

root
|_parent
|_leaf

I can only see the line coverage enabled at leaf whereas I want it at parent too.

Is there a depth switch missing in my build?
Any response is appreciated.
 

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