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  1. #1
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    polygon pour on top layer beneath BGA

    Hi,

    I am intending to design PCB using BGA IC, I am wondering whether is it not good if I use polygond copper right beneath the BGA package? Why?
    Thank you.

    Best regards,

    RH

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    Re: polygon pour on top layer beneath BGA

    Hi,

    What BGA pitch is it to have that much space?

    Klaus



    •   Alt20th April 2017, 17:24

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    Re: polygon pour on top layer beneath BGA

    It is FPGA



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    Re: polygon pour on top layer beneath BGA

    Hi,

    give useful informations.

    Klaus



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    Re: polygon pour on top layer beneath BGA

    Hi,

    so it is like this there are many vcc, vccd_pll, etc. So like GND they are near each other and I am wondering whether it is ok to connect them using polygon.
    If it is not enough what kind of information should i provide.

    Thank you,

    RH



    •   Alt21st April 2017, 09:18

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    Re: polygon pour on top layer beneath BGA

    Do you mean power planes below the BGA, common practice, suppress inner layer lands but add 0.15mm overdrill if your system supports it to get the thickest web between vias.

    Suggest you have a look at this...
    http://www.aetpcb.com/aet/net_resour...nd_Routing.pdf



  7. #7
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    Re: polygon pour on top layer beneath BGA

    The question title suggests you want to a copper pour connecting multiple adjacent BGA balls. That's surely possible.

    A side effect is however that BGA pads inside a copper pour become larger than others because they are effectively solder mask defined pads. Usually that's no problem in reflow solder.

    You see the effect with a BGA power IC (0.8 mm pitch) that has some pads on a copper pour:

    Click image for larger version. 

Name:	BGA+copper pour.jpg 
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  8. #8
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    Re: polygon pour on top layer beneath BGA

    are the pad sizes suppose to be different on that example?



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    Re: polygon pour on top layer beneath BGA

    All BGA pads have nominal 0.4 mm diameter (NSMD), the isolated pads are actually etched down to about 0.35 mm. The pads inside a copper pour are effectively solder mask defined to nominal 0.5 mm, actually 0.57 mm.



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    Re: polygon pour on top layer beneath BGA

    Just curious, cheers.



    •   Alt25th April 2017, 14:28

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  11. #11
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    Re: polygon pour on top layer beneath BGA

    Apart from PCB manufacturing tolerances (or possibly intentional modifications by the PCB house) visible in the example, it's exactly what you can expect when placing BGA pads on a copper pour (or traces wider than the pad).

    I understood the original question so that the OP intends something similar, thus I showed this real world example to illustrate possible side effects.

    In the present design, the copper pour is preferred to achieve low connection resistance for a switch mode regulator. I agree that the pad finish look curious, but I feel that it's still the best option in this case.



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    Re: polygon pour on top layer beneath BGA

    Firstly I always follow the IPC 7351 recomendation of 1:1 for solder resist openings, allowing the manufacturer to open the resist enough to get a good yield rate but avoid solder resist encroachment on pads. When solder mask defined pads come into the equation even more care is needed both from the manufacturer and the designer. If not then you can suffer bad solder joints on you BGA due to the differences in pad sizes... Round BGAs the extra added to the solder resist opening should be pretty minor to avoid exposure of copper to avoid solder shorts.



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