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How to export Xilinx generated schematic ot EDIF format?

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dragonwell

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edif format

Hi,

Who know how to conver the XST synthesised schematic .ngr format to EDIF format?


Thx!

Piers
 

ngc2edif

I don't think you want to do that. The NGR is an optional file intended only for the RTL viewer.
The normal procedure is XST spits out an NGC file, which you then feed into NGC2EDIF.
 

xilinx ngc ngr

The resultant EDIF from ngc2edif is for simulation purposes..

See links:
https://www.fpga-faq.org/archives/70475.html#70481
https://www.fpga-faq.org/archives/58175.html#58181

ngc2edif.exe is for simulation only and is the same as the xst edifngc
paramter. ISE 4 was the last version to include the ability to compile to
EDIF.

ISE 4.2 XST supported compile to EDIF but, unfortunately, they dropped that
parameter with the newer versions
Click to expand...
Code: 
C:\>ngc2edif
Usage: ngc2edif [-bd <busformat>] [-log <log_file>] [-quiet] [-w] <infile>
[<outfile>]
   -bd <bus_format>  Specify the bus delimiter to be used in the output edif.
                     The argument bus_format is required and could be of type
                         angle (bus notation would be bus<msb:lsb>
                         paren (bus notation would be bus(msb:lsb)
                         square (bus notation would be bus[msb:lsb]
                         none (generate buses without delimiters, busmsb:lsb
                     If -bd is not used, then the bus delimiters in the input
                     NGC file would be preserved.
   -log log_file     Specify log file (Default is ngc2edif.log).
   -quiet            Reduce screen output.
   -w                Overwrite the output file
   <infile>          Input File: '.ngc'.
   <outfile>         Output file name.  Default is '<ngcfile>.ndf'

ngc2edif translates an NGC file into an EDIF netlist which is intended for use
within supported synthesis tools as a means of determining resource / timing
estimates. The EDIF is defined in terms of Xilinx Library Primitives (Unisims).
 

ise rtl schematic export

Yes, that's correct.

Dragonwell didn't say why he wanted the EDIF.

My ISE flow: Verilog -> xst -> ngdbuild -> map -> par -> trce -> bitgen.

During simulation I don't care about timing, so I simply feed my HDL straight into ModelSim.
 

xilinx edif output

I need the sch for layout tool, synthesizer is too expensiver, anyone knows a free one?

Thx!
 

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