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  1. #1
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    How FPGAs are refreshing the logic

    Hi,

    It may be a dumb question, but I am very curios in how FPGA are refreshing the logic after configuration is done.
    Since I didnt find any information about it, I am interested if the CRAM from FPGAs is setting the logic only one time, after reconfiguration, or the logic is set always at a specific amount of time or clocks. My guess is that the CRAM is refreshing the logic every time.

    I am interested for the 7 Family FPGAs from Xilinx. If somebody knows the answer or maybe he can show me a documentation will be great.

    Cheers,
    Vlad
    I am a bad guy, but I have good intentions!

    •   Alt20th April 2017, 09:14

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  2. #2
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    Re: How FPGAs are refreshing the logic

    What do you exactly mean with "refreshing the logic"?



    •   Alt20th April 2017, 14:11

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  3. #3
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    Re: How FPGAs are refreshing the logic

    Almost all modern FPGA's are SRAM based.
    Once loaded, SRAM will erase upon power off.
    However, SRAM doesn't "leak" its charge as DRAM would. Hence, it doesn't require refreshing.

    Look at the construction of an SRAM cell:
    https://en.wikipedia.org/wiki/Static...-access_memory



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