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How FPGAs are refreshing the logic

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Vlad.

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Hi,

It may be a dumb question, but I am very curios in how FPGA are refreshing the logic after configuration is done.
Since I didnt find any information about it, I am interested if the CRAM from FPGAs is setting the logic only one time, after reconfiguration, or the logic is set always at a specific amount of time or clocks. My guess is that the CRAM is refreshing the logic every time.

I am interested for the 7 Family FPGAs from Xilinx. If somebody knows the answer or maybe he can show me a documentation will be great.

Cheers,
Vlad
 

What do you exactly mean with "refreshing the logic"?
 

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