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    Xilinx: 7 series FPGA Transreceiver

    Could any one please tell me the crieteria to select Line rate and their corresponding reference frequency and what is DRP frequency.

    •   Alt19th April 2017, 21:20

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    Re: Xilinx: 7 series FPGA Transreceiver

    The line rate and the reference frequency used are explained in the documentation for the transceivers, it's typically a factor of 20*Fref (or maybe 10) for lower line rates and 40*Fref for higher line rates.

    e.g. 3.125G uses either a 156.25MHz (20:1) or a 312.5MHz (10:1)


    The DRP (dynamic reconfiguration port) clock frequency can't be any higher than the device configuration clock, which I believe the upper limit is 100 MHz in the 7 series.



    •   Alt19th April 2017, 21:30

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    Re: Xilinx: 7 series FPGA Transreceiver

    Quote Originally Posted by ads-ee View Post
    The line rate and the reference frequency used are explained in the documentation for the transceivers, it's typically a factor of 20*Fref (or maybe 10) for lower line rates and 40*Fref for higher line rates.

    e.g. 3.125G uses either a 156.25MHz (20:1) or a 312.5MHz (10:1)


    The DRP (dynamic reconfiguration port) clock frequency can't be any higher than the device configuration clock, which I believe the upper limit is 100 MHz in the 7 series.

    Thanks ads-ee for prompt response and explanation.

    So as per equation 20*Fref we are calculating line rate as per available frequency in vivado (for example) e.g. 156.25 *20 = 3.125G but if i have 40G seres and using 4 lanes , i.e. 10.3125G per lane , as per equation 10.3125/20 = 515.625 MHz, it means i need to choose 515.625 MHz as a reference clock which seems to be very high.

    and does this reference clock depend upon hardware support e.g. QSFP used to provide reference clock to serdes if QSFP doesn't support such a high frequency like in my case QSFP supports 100 and 156.25 MHZ reference frequency only what cold be the available options for us.

    could you please share some documentation which can help me further in this context.



    •   Alt20th April 2017, 00:48

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    Re: Xilinx: 7 series FPGA Transreceiver

    I think you're misinterpreting the 40G as a single lane, that is probably the total bandwidth the channel (4 physical lanes) supports. Virtex-7 can support 28.05 Gb/s line rate transceivers, though I'm not sure which version does this as I can only find that number in the 7 series overview document (ds180).

    The rates and the input clocks and PLL output clocks are defined by the equations in UG476 (v1.12) on page 48. Equation 2-1 and Equation 2-2 tell you how to calculate the PLL clock output from a reference clock and how to get the line rate based on that PLL clock output.

    There is also a table of CPLL settings for a bunch of common protocols (page 51), though there isn't a specific line for a 10Gb/s line rate. As you'll notice there are a bunch of N1 & N2 factors that are 10 or 20, which is where I mentioned those numbers. I recall that the ones in the ultrascale line are higher as they have really fast transceivers.

    You really need to download the UG476 and read it otherwise you'll likely end up with a non-functional design if you just try to do this without knowing all the details.



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