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    [moved] Dual MicroBlaze design in Xilinx EDK 10.1

    It is not possible to create a system design comprising of two MicroBlaze processors operating at the same time. I used the base system builder wizard in Xilinx EDK 10.1 to design the system. Initially I built a single processor system and then tried to add the second processor IP (from IP catalog). But when creating the netlist for the system the following error occured:

    Performing IP level DRCs on properties...

    Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...
    ERROR:MDT - issued from TCL procedure
    "::hw_microblaze_v7_10_a::check_iplevel_settin gs" line 6
    microblaze_1 (microblaze) - The CLK signal is not connected. MicroBlaze
    cannot work without a correct CLK signal input.
    ERROR:MDT - platgen failed with errors!
    Done!
    The issue I suppose was with clock signal not connected to the processor IP. I didn't find any options to connect the same. What might I be doing wrong??

    P.S: the processors are not intended to be used as multi-cores. They should be individually operating embedded processors

    •   Alt19th April 2017, 05:39

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    Re: [moved] Dual MicroBlaze design in Xilinx EDK 10.1

    There is nothing in Xilinx's tool chain AFAIK that precludes having multiple Microblaze processors in a design, Carefully check that you have a clock connected to both Microblaze.



    •   Alt19th April 2017, 17:00

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    Re: [moved] Dual MicroBlaze design in Xilinx EDK 10.1

    For your information, 2 MB MCS can be used on vivado.
    To improve one's brain, the doors are needed over the keys.



    •   Alt20th April 2017, 10:46

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    Re: [moved] Dual MicroBlaze design in Xilinx EDK 10.1

    how can I check for the connection?
    the ports tab in system assembly view window doesn't show any clock signal connections. also for my design the BSB generated a clock generator and sys_proc_reset module.

    should I manually modify the MHS file to pt in necessary clock signals for the processors?

    - - - Updated - - -

    Quote Originally Posted by ads-ee View Post
    There is nothing in Xilinx's tool chain AFAIK that precludes having multiple Microblaze processors in a design, Carefully check that you have a clock connected to both Microblaze.
    how can I check for the connection?
    the ports tab in system assembly view window doesn't show any clock signal connections. also for my design the BSB generated a clock generator and sys_proc_reset module.

    should I manually modify the MHS file to pt in necessary clock signals for the processors?



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    Re: [moved] Dual MicroBlaze design in Xilinx EDK 10.1

    Quote Originally Posted by roshan12 View Post
    should I manually modify the MHS file to pt in necessary clock signals for the processors?
    Do that as a test, and then read the new mhs-file back into the EDK tool.
    Maybe you can see the clock signal and understand what mistake you did.
    Then go back to your original mhs file and try to do the same thing.



    •   Alt21st April 2017, 16:56

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    Re: [moved] Dual MicroBlaze design in Xilinx EDK 10.1

    Quote Originally Posted by std_match View Post
    Do that as a test, and then read the new mhs-file back into the EDK tool.
    Maybe you can see the clock signal and understand what mistake you did.
    Then go back to your original mhs file and try to do the same thing.
    Hi, when i checked the MHS file the Microblaze instances were mapped as follows:

    BEGIN microblaze
    PARAMETER INSTANCE = microblaze_0
    PARAMETER C_INTERCONNECT = 1
    PARAMETER HW_VER = 7.10.a
    PARAMETER C_DEBUG_ENABLED = 1
    BUS_INTERFACE DLMB = dlmb_0
    BUS_INTERFACE ILMB = ilmb_0
    BUS_INTERFACE DPLB = mb_plb_0
    BUS_INTERFACE IPLB = mb_plb_0
    BUS_INTERFACE DEBUG = microblaze_0_dbg
    PORT MB_RESET = mb_reset
    PORT Interrupt = xps_timer_0_Interrupt

    ...............


    BEGIN microblaze
    PARAMETER INSTANCE = microblaze_1
    PARAMETER HW_VER = 7.10.a
    BUS_INTERFACE DEBUG = microblaze_1_dbg
    BUS_INTERFACE IPLB = mb_plb_1
    BUS_INTERFACE DPLB = mb_plb_1
    BUS_INTERFACE ILMB = dlmb_1
    BUS_INTERFACE DLMB = ilmb_1
    PORT MB_RESET = mb_reset
    PORT INTERRUPT = xps_timer_1_Interrupt
    the lines PARAMETER C_INTERCONNECT = 1 and were found to be missing in the Microblaze IP added afterwards.

    I also tried to add an additional clock output to the clock generator.

    what might i be missing?



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