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[move] setup/hold time of logic gates

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oAwad

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Hello all,

regarding setup/hold time of a logic cell (ex. DFF)...In case of input logic '1', is the definition of setup/hold time is that input should be constant (voltage wise not logic wise) during this time or generally greater than cell threshold voltage ? (so maybe varying but still above cell threshold)
 

Re: setup/hold time of logic gates

At the lowest levels, propagation delay of a stage
depends on the "overdrive" (above / below threshold).
Exactly -at- threshold the delay is by definition
infinite. So you will often see a maximum transition
time specified for an input, as a condition of the
prop delay spec.

Slow moving inputs will need more setup time. How
much, is rarely spec'd "beyond the box" and would
be pretty conditions-variable.
 

Re: setup/hold time of logic gates

Hello all,

regarding setup/hold time of a logic cell (ex. DFF)...In case of input logic '1', is the definition of setup/hold time is that input should be constant (voltage wise not logic wise) during this time or generally greater than cell threshold voltage ? (so maybe varying but still above cell threshold)

for standard cell characterization, Vth is not taken into account like that. setup is with respect to signals transition full swing, from 0 to VDD, not from 0 to Vth.
 
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    oAwad

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Re: setup/hold time of logic gates

for standard cell characterization, Vth is not taken into account like that. setup is with respect to signals transition full swing, from 0 to VDD, not from 0 to Vth.

That's what I'm looking for. So in order to change setup/hold to be depending on 0 to Vth for a certain application, I have to modify the design on DFF (in Spice netlist) or I can just tune the building transistors' parameters ? (transistor model)
 

Re: setup/hold time of logic gates

You need to generate a new .lib file, which can be quite complicated. Some spice-like simulations can help you fake a .lib file, assuming both VDD and Vth are the same value. No need for design modification, just set the voltage levels accordingly on the spice simulation. Results, however, can be very poor. There's a reason digital design doesn't operate in deep subthreshold.
 

Re: setup/hold time of logic gates

You need to generate a new .lib file, which can be quite complicated. Some spice-like simulations can help you fake a .lib file, assuming both VDD and Vth are the same value. No need for design modification, just set the voltage levels accordingly on the spice simulation. Results, however, can be very poor. There's a reason digital design doesn't operate in deep subthreshold.

Actually I'm doing this modification just for one DFF cell that I'm using in my design. By changing the .lib file, I understand that if I want to operate the DFF according to Vth, you mean just decrease setup/hold time of the DFF (so it doesn't depend on the schematic of DFF). My understanding is that setup/hold timing in .lib file only affects "AD", "AS","PD","PS" capacitances for each transistor in my spice netlist, so by decreasing these capacitances in each transistor in my DFF subckt, I will be able to operate the DFF according to Vth.

Please correct me if I'm wrong.

Here is the schematic of the DFF

Capture.PNG

Many thanks !
 

A designer should not change the transistor model, not
unless he has control over the process and plenty of
time to wait.

Unless you have no intention of delivering a real and
functioning product, then lie all you want about what
the transistors are like.
 

A designer should not change the transistor model, not
unless he has control over the process and plenty of
time to wait.

Unless you have no intention of delivering a real and
functioning product, then lie all you want about what
the transistors are like.

I'm actually an undergraduate student practicing VLSI so no fabrication constraints involved. Thanks ;)
 

I'm trying to operate a DFF gate by crosstalk (as part of my hardware security class in Uni) so as you can find in the attached simulation, the DFF_input is the victim and capacitively coupled to the aggressor. I would like to modify the DFF so as to operate on this crosstalk voltage...so for example if crosstalk voltage surpassed DFF threshold voltage (to be modified...let's say 0.1V), then DFF outputs logic '1' else outputs logic '0'.
q3.PNG

One point to add, you can see in the attached simulation that DFF_input drops quickly (177.7mV then the next point is 158.6mV), so that's why I was asking about setup/hold time.

What I did so far is that I removed "AD", "AS", "PD", "PS" from all transistors in DFF subckt (from my understanding that this should remove the sense of setup/hold time of DFF....not sure though), but didn't work in simulation. I'm missing the methodology how to start.

Note: I'm allowed to change any parameters (except VDD..it's constant 1.1V) so no fabrication constraints, but for sure with understanding the fabrication/physical impact of my modification.

Here is the DFF subckt:
Code:
.subckt DFF_X1_2 D CK QN VSS VDD Q
M_MN2 ci cni VSS VSS NMOS_victim L=5e-08 W=2.1e-07 
M_MN6 VSS z4 z6 VSS NMOS_victim L=5e-08 W=9e-08
M_MN7 z3 ci z6 VSS NMOS_victim L=5e-08 W=9e-08
M_MN4 z2 cni z3 VSS NMOS_victim L=5e-08 W=2.75e-07
M_MN3 z2 D VSS VSS NMOS_victim L=5e-08 W=2.75e-07
M_MN5 z4 z3 VSS VSS NMOS_victim L=5e-08 W=2.1e-07
M_MN1 VSS CK cni VSS NMOS_victim L=5e-08 W=2.1e-07
M_MN8 z12 z3 VSS VSS NMOS_victim L=5e-08 W=2.1e-07
M_MN9 z9 ci z12 VSS NMOS_victim L=5e-08 W=2.1e-07
M_MN12 z9 cni z8 VSS NMOS_victim L=5e-08 W=9e-08
M_MN11 z8 z10 VSS VSS NMOS_victim L=5e-08 W=9e-08
M_MN10 VSS z9 z10 VSS NMOS_victim L=5e-08 W=2.1e-07
M_MN14 QN z9 VSS VSS NMOS_victim L=5e-08 W=4.15e-07
M_MN13 VSS z10 Q VSS NMOS_victim L=5e-08 W=4.15e-07
M_MP2 ci cni VDD VDD PMOS_victim L=5e-08 W=3.15e-07
M_MP6 VDD z4 z1 VDD PMOS_victim L=5e-08 W=9e-08
M_MP7 z1 cni z3 VDD PMOS_victim L=5e-08 W=9e-08
M_MP4 z3 ci z5 VDD PMOS_victim L=5e-08 W=4.2e-07
M_MP3 z5 D VDD VDD PMOS_victim L=5e-08 W=4.2e-07
M_MP5 z4 z3 VDD VDD PMOS_victim L=5e-08 W=3.15e-07
M_MP1 VDD CK cni VDD PMOS_victim L=5e-08 W=3.15e-07
M_MP8 z7 z3 VDD VDD PMOS_victim L=5e-08 W=3.15e-07
M_MP9 z9 cni z7 VDD PMOS_victim L=5e-08 W=3.15e-07
M_MP12 z9 ci z11 VDD PMOS_victim L=5e-08 W=9e-08
M_MP11 z11 z10 VDD VDD PMOS_victim L=5e-08 W=9e-08
M_MP10 VDD z9 z10 VDD PMOS_victim L=5e-08 W=3.15e-07
M_MP14 QN z9 VDD VDD PMOS_victim L=5e-08 W=6.3e-07
M_MP13 VDD z10 Q VDD PMOS_victim L=5e-08 W=6.3e-07
.ends

and here is the CMOS transistor model I'm using:
Code:
* Customized PTM 45nm NMOS
.model  NMOS_victim  nmos  level = 54
+version = 4.0    binunit = 1    paramchk= 1    mobmod  = 0
+capmod  = 2      igcmod  = 1    igbmod  = 1    geomod  = 1
+diomod  = 1      rdsmod  = 0    rbodymod= 1    rgatemod= 1
+permod  = 1      acnqsmod= 0    trnqsmod= 0

* parameters related to the technology node
+tnom = 27    epsrox = 3.9
+eta0 = 0.0049    nfactor = 2.1    wint = 5e-09
+cgso = 1.1e-10    cgdo = 1.1e-10    xl = -2e-08

* parameters customized by the user
+toxe = 1.75e-09    toxp = 1.1e-09    toxm = 1.75e-09    toxref = 1.75e-09
+dtox = 6.5e-10    lint = 3.75e-09
+vth0 = 0.424    k1 = 0.489    u0 = 0.04698    vsat = 147390
+rdsw = 155    ndep = 2.81e+18    xj = 1.4e-08
+k2      = 0.2 

* Customized PTM 45nm PMOS
.model  PMOS_victim  pmos  level = 54
+version = 4.0    binunit = 1    paramchk= 1    mobmod  = 0
+capmod  = 2      igcmod  = 1    igbmod  = 1    geomod  = 1
+diomod  = 1      rdsmod  = 0    rbodymod= 1    rgatemod= 1
+permod  = 1      acnqsmod= 0    trnqsmod= 0

* parameters related to the technology node
+tnom = 27    epsrox = 3.9
+eta0 = 0.0049    nfactor = 2.1    wint = 5e-09
+cgso = 1.1e-10    cgdo = 1.1e-10    xl = -2e-08

* parameters customized by the user
+toxe = 1.85e-09    toxp = 1.1e-09    toxm = 1.85e-09    toxref = 1.85e-09
+dtox = 7.5e-10    lint = 3.75e-09
+vth0 = -0.383    k1 = 0.457    u0 = 0.00496    vsat = 70000
+rdsw = 155    ndep = 2.2e+18    xj = 1.4e-08
+k2      = -0.2

Many thanks!
 
Last edited:

I think you are way way way off target here. setup and hold are characteristics of flops, they are not in the netlist. Whatever you removed, I think that is part of the flop and should be put back. Go check with the documentation what the meaning of AD/AS/... is. I am almost sure that is drain area.
 

I think you are way way way off target here. setup and hold are characteristics of flops, they are not in the netlist. Whatever you removed, I think that is part of the flop and should be put back. Go check with the documentation what the meaning of AD/AS/... is. I am almost sure that is drain area.

Thanks for your reply. I checked "AD" and yes it's the drain area...but wouldn't the drain/source area control the gate-drain/gate-source/drain-source parasitic capacitance ? I mean without including parasitics of interconnect, what else can cause setup/hold timing constraints ?

and as you said before, if setup time is related to full swing in std cells, then I'll never reach setup (as my DFF_input has around 0.2V peak voltage)...so if I can relate setup/hold to Vth instead of VDD, then I think I'll reach the target. To achieve this, do I need to change the DFF subckt or tune the transistors parameters ?

Please if you have some suggestions to reach the target, I'll be grateful!
 

Setup/hold are architecture dependent.

So from you answer, can I understand that I need to change the std cell DFF to a simpler one ? (for lower setup/hold) and at the same time tune transistors for lower threshold ?
 

You would need your crosstalk "aggressor" coupling
capacitance to overmatch or well exceed the "victim"
node shunt capacitance (wire, and sum of driver Cds
and receiver N*(Cgs+Cgd) presuming the victim is at
rest, fully driven) along with the losses to the
"victim's" driver's on resistance and the limitations of
the "agressor" source impedance.

A valid simulation would represent all of these. And
then you would see "nothing to see" except for the
case that the "victim" is proceeding through its input
transition, where the "aggressor" can beat the delay
forward or back, cause a S/H violation and false
clocking of data, metastability, or enough jitter to
ruin something downstream that cares about timing
accuracy. Have seen that, but it took two lines
routed ~2500um adjacent at min spacing to do it.

"Trusted microelectronics" is full of vapor-pushers
looking for a problem they can pretend to solve. My
old university has one of my former undergrad teaching
assistants now the dean of the electrical engineering
department and putting his name on papers so full
of technical errors, outright lies and groveling for
further federal funding, it's an embarrassment.

But meanwhile you have a course to pass, so you
probably do not want to think about or discuss the
futility of it all. Especially with someone whose tenure
track depends on said groveling.
 

If I understand correctly what you are doing, all you need to do is to increase the crosstalk cap. The glitch height will be higher and then it can have change to be latched in.
 

If I understand correctly what you are doing, all you need to do is to increase the crosstalk cap. The glitch height will be higher and then it can have change to be latched in.

Yes for sure, but since this simulation models a part of a VLSI physical layout that I already made, so I'm bound in this case with a minimum separation-gap/coupling-length between aggressor and victim, so I still can increase coupling capacitance but not too much.....so it would be much easier for me to weaken the DFF to accept this crosstalk voltage.

Thanks for your reply
 

It would be valid to run a series of coupling cap values
to determine a layout coupling margin. Likewise valid
to vary VIH / VIL to determine an as-laid-out noise
margin. This may be your likeliest way to "weaken"
the flip-flop (internal device attributes would vary
only with a pretty constrained range, and only the
front end of the clock fork matters to this exercise.
 

It would be valid to run a series of coupling cap values
to determine a layout coupling margin. Likewise valid
to vary VIH / VIL to determine an as-laid-out noise
margin. This may be your likeliest way to "weaken"
the flip-flop (internal device attributes would vary
only with a pretty constrained range, and only the
front end of the clock fork matters to this exercise.

Thank you Sir for your help. Is there a way to know VIH/VIL for the DFF other than hand analysis of the DFF schematic ?

and should I estimate Vth of DFF to be Vth of NMOS or PMOS highlighted in the following DFF schematic ?
DFF.PNG

I have tried varying coupling capacitance value in the netlist (manually), but it didn't work in simulation.

I'm attaching NMOS & PMOS models I'm using for the DFF, may be you see something I don't see it. (left is PMOS and right is NMOS)
PMOS.PNGyarab1.PNG

Many thanks!
 

You are showing ID-VD curves, you need to look at ID-VG
(or sqrt(ID) vs VGS), to extrapolate the slope to 0 which is
your model VT, second order effects aside).

When you say coupling cap variation "didn't work", does
that mean failed to cause failure? Or made no difference
to victim-trace perturbation amplitude? The latter would
be a simulation setup / netlist problem; the former may
simply mean the DFF is robust to the threat.

You do not need to know VIH, VIL a priori; you would put
the DFF to a known state, move D to the opposite state,
and then move the clock from its fully driven VIL (=vss)
incrementally upward repeating the clock line perturbation
(through the coupling model) in a parametric outer loop,
to see at what VIL the clock pin becomes sensitive enough
to flip. Presuming this is a positive edge triggered DFF.

Then you might also test the clock, remaining in its high
state, change the data, relax clock VIH level from =vdd
downward, apply a negative-going impulse and see where
that causes a false-clock result.
 

Yes for sure, but since this simulation models a part of a VLSI physical layout that I already made, so I'm bound in this case with a minimum separation-gap/coupling-length between aggressor and victim, so I still can increase coupling capacitance but not too much.....so it would be much easier for me to weaken the DFF to accept this crosstalk voltage.
Thanks for your reply

Now, can you firstly force a pulse at the input D pin of DFF ?
You need to make sure where is the pulse's height/width that logic can be latched by DFF.

Then, with that working force voltage, let change the cap inside the DFF model.
You can use a loop to vary such input info and open then waveform to check case by case.

Then, you can find out how the inside cap affect to DFF operation corresponded to a input glitch at D pin ( with a specific timing, width and height )

This is not a solution, but I may do this if I were you to investigate deeper.
 

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