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  1. #1
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    frequency divider using counter

    Hi ALL,

    I need a clarification regarding frequency divider using counter.

    Usually, If a counter with N bits, it will divide the frequency by 2^N.
    Code Verilog - [expand]
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    reg [19:0] counter;
     
       always@(posedge clk)  // clock frequency is 100MHZ
        begin 
            if(!reset_n)
                counter <= 0;
            else
            begin
                counter <= counter + 1'b1;
                clock   <= counter[16];
            end
        end

    From the above snippet, what will be the frequency of "clock"
    Last edited by ads-ee; 18th April 2017 at 15:27. Reason: Added syntax tags

    •   Alt18th April 2017, 10:41

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  2. #2
    Full Member level 3
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    Re: frequency divider using counter

    Quote Originally Posted by viyaaloth View Post
    Hi ALL,

    I need a clarification regarding frequency divider using counter.

    Usually, If a counter with N bits, it will divide the frequency by 2^N.

    reg [19:0] counter;

    always@(posedge clk) // clock frequency is 100MHZ
    begin
    if(!reset_n)
    counter <= 0;
    else
    begin
    counter <= counter + 1'b1;
    clock <= counter[16];
    end
    end

    From the above snippet, what will be the frequency of "clock"
    hi

    approximately 763 Hz (accurately :: 762.93)

    regards


    1 members found this post helpful.

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