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How to remove DRC error and how to check in layout

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abhishekece

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ERRORS
1.Poly area must be o.1 µm.
In this problem how did i incease poly area and please tell me how did it adjust.
2.Nwell width must be 0.6 µm.
please explain it and please tell me how did it adjust.
3.Pimp to gate end enclosure must be 0.18µm.
please explain it and please tell me sir with conclusion.
 

Have you read the layout groundrules document for
the technology in question? These always (in my
experience) contain "cartoons" which show visually
the rule and the layers and relationships involved.

It's unlikely that poly area must be 0.1um. First, area
is square microns, not microns. Second, this is probably
a -minimum-, not an -equals-, unless you're in a very
low nanometers node with a single fixed geometry gate.

We have no idea what you did because you show
nothing.

DRC errors should display with highlighting of the
problem area. Compare this with the design rules
document illustrations and it should become more
evident, what the complaint is about.
 

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