barry
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We've come across a subtle, but vexing problem with the Analog Devices AD9858 Direct Digital Synthesis chip. The REFCLK input is 960 MHz (but this doesn't really matter). Our FPGA is running off a 10MHz clock which is synched to the 960MHz. There is a divide-by-eight counter in the AD9858 which divides the reference clock down to 120MHz (in our case) . We see that when we assert and release the reset (synched to the 10MHz), the 120MHz clock does not always start at the same time. In other words, relative to the 10MHz we will sometimes see the 120MHz clock start one 960MHz clock later than 'normal'. This manifests itself as our output signal starting at two different times relative to the FUD. But the time-shift only occurs after a reset. Every subsequent sweep will always start at the same relative time until another reset occurs. Stated another way, the output will shift by one 960MHz clock after a reset, but is consist from FUD to FUD, as long as a reset doesn't occur. I hope I've made this clear.
Has anyone experienced this? Do you have a solution? I've contacted Analog Devices, but they apparently can't find anyone who knows anything about this chip (it's a little old). I initially thought that our problem was due to the slow fall time of the reset signal relative to the 960Mhz signal, but the problem was still apparent even when I lowered the REFCLK frequency to 100MHz.
Thanks.
Has anyone experienced this? Do you have a solution? I've contacted Analog Devices, but they apparently can't find anyone who knows anything about this chip (it's a little old). I initially thought that our problem was due to the slow fall time of the reset signal relative to the 960Mhz signal, but the problem was still apparent even when I lowered the REFCLK frequency to 100MHz.
Thanks.