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    AD9858 DDS reset problem

    We've come across a subtle, but vexing problem with the Analog Devices AD9858 Direct Digital Synthesis chip. The REFCLK input is 960 MHz (but this doesn't really matter). Our FPGA is running off a 10MHz clock which is synched to the 960MHz. There is a divide-by-eight counter in the AD9858 which divides the reference clock down to 120MHz (in our case) . We see that when we assert and release the reset (synched to the 10MHz), the 120MHz clock does not always start at the same time. In other words, relative to the 10MHz we will sometimes see the 120MHz clock start one 960MHz clock later than 'normal'. This manifests itself as our output signal starting at two different times relative to the FUD. But the time-shift only occurs after a reset. Every subsequent sweep will always start at the same relative time until another reset occurs. Stated another way, the output will shift by one 960MHz clock after a reset, but is consist from FUD to FUD, as long as a reset doesn't occur. I hope I've made this clear.

    Has anyone experienced this? Do you have a solution? I've contacted Analog Devices, but they apparently can't find anyone who knows anything about this chip (it's a little old). I initially thought that our problem was due to the slow fall time of the reset signal relative to the 960Mhz signal, but the problem was still apparent even when I lowered the REFCLK frequency to 100MHz.

    Thanks.

    •   Alt18th April 2017, 00:40

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    Re: AD9858 DDS reset problem

    this reset is being generated by the FPGA and goes to the DDS, correct?

    Does your FPGA have OSERDES like Xilinx? You might be able to check the relative position of the reset release in relation to the REFCLK rising edge by using it to shift the reset using DRP. You might find there is a window where the reset always works in producing the same phase relationship between the 10 MHz and 120 MHz clocks. It may be that the delays in the I/O and the routing are placing the reset release edge at the worst possible position for the REFCLK rising edge. Once you find the correct dialed in value you can always adjust your I/O output constraint to permanently fix the issue.



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    Re: AD9858 DDS reset problem

    Quote Originally Posted by ads-ee View Post
    this reset is being generated by the FPGA and goes to the DDS, correct?

    Does your FPGA have OSERDES like Xilinx? You might be able to check the relative position of the reset release in relation to the REFCLK rising edge by using it to shift the reset using DRP. You might find there is a window where the reset always works in producing the same phase relationship between the 10 MHz and 120 MHz clocks. It may be that the delays in the I/O and the routing are placing the reset release edge at the worst possible position for the REFCLK rising edge. Once you find the correct dialed in value you can always adjust your I/O output constraint to permanently fix the issue.
    I don't have the ability to adjust the reset edge timing, BUT I am able to adjust the REFCLK phase relative to everything else. I was able to make things worse (3 different states instead of two) , but not better. I suspect that there is something inside the AD9858 as to how it resets that divide-by-eight counter, but only Analog Devices can answer that, and they're being pretty unresponsive about this.



    •   Alt18th April 2017, 16:29

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    Re: AD9858 DDS reset problem

    What is the granularity of your adjustments to REFCLK? Seems like you managed to move the relative position of reset to a much much worse position. Have your tried with a somewhat lower REFCLK so you have more leeway in the relative relationship?

    The response from AD is not encouraging...that is usually the response for an Oh...Sh!t someone's trying to use that feature that doesn't work kind of thing.



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    Re: AD9858 DDS reset problem

    I was using a continuously variable phase shifter on the 960, so I am able to set anything between 0-180 degrees. I did try lower frequencies and had the same issue. I initially thought the problem was the fall time of the reset signal was too long, i.e., it lasted over several clock cycles, but that theory seems to have been destroyed because I saw the problem when running as low as 100MHz. Further, I tried using an AD eval board to see if the problem existed there, too. What I observed was that although the problem was still there, it occurred much less frequently. And to further confuse me, the falling edge of the reset was significantly LONGER than on my actual board.

    I'm going to try to add a series resistor on my reset line. Maybe there's some reflection I'm not seeing.



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    Re: AD9858 DDS reset problem

    It's starting to sound more and more like a reset problem inside the AD9858, which is probably why you aren't getting much feedback from Analog Devices. Wonder they eventually come back with some work around solution to fix the problem.

    I suspect the normal usage of the part is to use the divider clock output to run external logic and not need it synchronized to an external clock using the reset. So I imagine your usage hasn't been thoroughly vetted, by previous customers.

    I wonder what their reset circuit looks like for the clock divider. Maybe they have some skew issues with the reset on the bit-0 of the divider (if they use a counter for that divider).



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    Re: AD9858 DDS reset problem

    Quote Originally Posted by ads-ee View Post
    It's starting to sound more and more like a reset problem inside the AD9858, which is probably why you aren't getting much feedback from Analog Devices. Wonder they eventually come back with some work around solution to fix the problem.

    I suspect the normal usage of the part is to use the divider clock output to run external logic and not need it synchronized to an external clock using the reset. So I imagine your usage hasn't been thoroughly vetted, by previous customers.

    I wonder what their reset circuit looks like for the clock divider. Maybe they have some skew issues with the reset on the bit-0 of the divider (if they use a counter for that divider).
    That's my suspicion as well, that's there's some internal issue that AD is not publishing. Since this is an older part it may be that the original designer is dead. (Or should be.)



    •   Alt18th April 2017, 19:02

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    Re: AD9858 DDS reset problem

    Quote Originally Posted by barry View Post
    That's my suspicion as well, that's there's some internal issue that AD is not publishing. Since this is an older part it may be that the original designer is dead. (Or should be.)
    Or left the company before someone found the problem (you). Unfortunate for you nobody else found it earlier before the designer left.



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