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storing values in array

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ecasha

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Hi, I wrote code for storing output values in an array.There are 6 outputs.For different cases, 6 outputs are to be stored in consecutive locations without altering previous values.Like in the first case 6 outputs are stored in first 6 locations in the second case in nex 6 locations. I have written code which is given below. But When I simulate it values are overlapping.How do I rectify it
Code:
module array (SLT,out1,out2,out3,out4,out5,out6,farray);
input out1,out2,out3,out4,out5,out6;
input [1:0]SLT;
output [0:23]farray;
reg [0:23]farray;
reg tmp1,tmp2,tmp3,tmp4,tmp5,tmp6,tmp7,tmp8,tmp9,tmp10,tmp11,tmp12,tmp13,tmp14,tmp15,tmp16,tmp17,
tmp18,tmp19,tmp20,tmp21,tmp22,tmp23,tmp24;
initial farray= 0;
always @(SLT,out1,out2,out3,out4,out5,out6) begin
case (SLT)
 2'b00:begin 
 tmp1=out1; tmp2=out2; tmp3=out3; tmp4=out4; tmp5=out5; tmp6=out6;
 tmp7= 1'b0;tmp8=1'b0;tmp9=1'b0;tmp10=1'b0;tmp11=1'b0; tmp12=1'b0;
 tmp13=1'b0;tmp14=1'b0;tmp15=1'b0;tmp16=1'b0;tmp17=1'b0;tmp18=1'b0;tmp19=1'b0;tmp20=1'b0;tmp21=1'b0;tmp22=1'b0;tmp23=1'b0;tmp24=1'b0;
 end
2'b01 :begin
 tmp7=out1;tmp8=out2; tmp9=out3;tmp10=out4;tmp11=out5; tmp12=out6;
 tmp13=0;tmp14=1'b0;tmp15=1'b0;tmp16=1'b0;tmp17=1'b0;tmp18=1'b0;tmp19=1'b0;tmp20=1'b0;tmp21=1'b0;tmp22=1'b0;tmp23=1'b0;tmp24=1'b0; end  
 2'b10:begin
tmp13=out1;tmp14=out2;tmp15=out3;tmp16=out4;tmp17=out5;tmp18=out6;tmp19=1'b0;tmp20=1'b0;tmp21=1'b0;tmp22=1'b0;tmp23=1'b0;tmp24=1'b0;end
2'b11:  begin 
tmp19=out1;tmp20=out2;tmp21=out3;tmp22=out4;tmp23=out5;tmp24=out6;end
endcase
farray[0]=tmp1;
farray[1]=tmp2;
farray[2]=tmp3;
farray[3]=tmp4;
farray[4]=tmp5;
farray[5]=tmp6;
farray[6]=tmp7;
farray[7]=tmp8;
farray[8]=tmp9;
farray[9]=tmp10;
farray[10]=tmp11;
farray[11]=tmp12;
farray[12]=tmp13;
farray[13]=tmp14;
farray[14]=tmp15;
farray[15]=tmp16;
farray[16]=tmp17;
farray[17]=tmp18;
farray[18]=tmp19;
farray[19]=tmp20;
farray[20]=tmp21;
farray[21]=tmp22;
farray[22]=tmp23;
farray[23]=tmp24;
end 
endmodule
Plese tell me where I did the mistake.
 

What do you mean by the values are overlapping? What output are you getting, what output are you expecting to get?
 

The entire code looks like one big mistaken understanding of Verilog.

The so-called array isn't a memory, what you described is a combonational circuit with incomplete definition in each branch of the case resulting in the creation of latches. That is not a good design practice, latches for one thing are much harder to constrain than a simple clock period constraint.

Naming inputs out1-6 seems like a big mistake as it doesn't really relate well with the direction of the ports.

The fact that the outputs for the lower 6-bits take on the values updated for the next 6-bits is probably due to a scheduling problem at the time you change both the inputs (out1-6) and the SLT input. The always block is entered on changes in the out1-6 inputs, before the SLT input has been detected to have changed. Therefore the old SLT input is used to update the latches for the lower 6-bits. When the SLT input change is detected the always block then updates the next 6-bits with the same values in the new SLT location.

This code is just terrible. You need to read a good Verilog book and/or read a better tutorial site.
 

Another module's 6 outputs, i am sending it to this array.These output values should be stored based on SLT line.like in the first case, 6 outputs are stored in first 6 locations in the second case in next 6 locations.But in the secong case when slt =01 out1-6 are storing in first 6 locations of farray.But it should store in next 6 location of array i.e from farray[6] to farray[11] without changing the values of farray[0] to farray[5]

- - - Updated - - -

please tell me how to correct it.
 

please tell me how to correct it.

By not treating Verilog as a software language. If you want to store something use flip-flops and an enable to load the value. Either that or use a RAM to store the array.

Coders who treat Verilog like software usually end up with dismally performing hardware (typically giant combonational circuits), unsynthesizable code, latches (like your code), etc.
 

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