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spartan6 enable input signal remains latched

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moro

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Hello all,

i started out a uart tx module for sending a packet of 4bytes ( one at a time).... the data is sent ok, but i am facing some strange behaviour


My problem is on the enable signal, i hooked the enable of the uart module to a button on my board, also connected a LED in the logic to have a "visible feel"

If i press the button once, i expect some uart action, but if i release the button the uart should be stoped... but its not....

the LED is lighted and with a logic analyzer i have continous data when the button is not pressed !!

Its like the enable input remains latched in Hi state... and i wonder why? Is there a problem in my code? i did some simulation in ISE but there everything is working as expected

I highlighted the problem in my code bellow

here is my top module


Code:
module main_module(
output uart_out , // uart  tx line
input  clk,
input button,
output LD2
 );

parameter [31:0] testing = 32'h 44332211;
	

// instatiate the uart module

uart4byte uuu(
  .uart_clock(clk),
  .data(testing),
  .enable(button), 
  .tx_out(uart_out),
  .led(LD2)  // output to led
  );
 

endmodule;

and my 32bit uart module

Code:
module uart4byte(
input uart_clock,
input [31:0] data,
[COLOR="#FF0000"]input enable, [/COLOR]
output reg tx_out,
output reg led
);

       
	parameter idle  = 3'b000; // 0
	parameter start = 3'b001; // 1
	parameter stop  = 3'b010; // 2
	parameter send  = 3'b011; // 3
	parameter clear = 3'b100; // 4
	
        reg [7:0] pos = 0;
	reg [7:0] ii = 0;
	reg [7:0] state      =0; // set initial 3bit register to 0value ( binary 000) ( idle)
	reg [7:0] index      =0; // bit index	
	
	
	initial begin
	   tx_out = 1;
	end
	


	

	always @(posedge uart_clock) begin
	    
						
			 case (state)
		      	
					
	          idle:
	              begin
			     tx_out    <=1'b1; // in idle the dataline is set to high
                             index     <=0; // reset bit index
                      
   						 [COLOR="#FF0000"] if(enable == 1) begin	 
		   				     	state <= start; // set  state for start(1)
							led<=1;
						   end
						   else begin
						           state <=idle;
							   led<=0;
   					           end[/COLOR]
		           end
					  
    start: // 1
	     begin
		          tx_out <=1'b0; // set dataline to low, this indicates start bit in uart communication
			 state <= send; // set next state for sending the 8bit data
	     end
		  
   send: //3
	    begin
		    
		 tx_out <= data[index+pos];
			            
                                    if(index < 7) begin // check to see if we sent all 8 data bits 
					  index <= index +1;//increment by 1
					  state <= send; // set next state for sending remaining bits
			             end
				      else begin // if we sent all the data bits do this... 
					   index <=0 ; // clear the index counter
					    state <= stop; // set next state for sending the stop bit
				     end
             end

     stop:
	    begin
		           tx_out<=1'b1; // set the dataline to high, indicating a stop bit
			   state <= clear; // set next state for clearing the data line
	    end
  
      clear: 
	    begin
	    tx_out<=1'b1; // set the dataline to high, indicating a stop bit
       
					 	
						 if((index+pos)== 31) begin
						  	pos<=0;
							state <= idle; // set next state for clearing the data line
					          end
				                  else begin
						     state<=start; // back to start
						     pos <=pos + 8; // increment by 8positions	 
				                 end
			  	
		end
     default:		
	  state <= idle;
	  endcase
	
end	

endmodule
 

Hi,

Show the schematic of button, Led, logic analyzer...how they are connected to the FPGA.

Did you take care about (unused) inputs: Don't let them floating.

Klaus
 

Hello Klaus,

the logic analyzer (salaee 16channel) is connected between ground and pin P7

i am using a small board from digilent cmod s6, i have atached the schematic, in the mean time bellow is my constrains file

NET "button" LOC="P9" | IOSTANDARD=LVCMOS33 ; // button 1
NET "uart_out" LOC="P7" | IOSTANDARD=LVCMOS33 ; // board pin4
NET "LD2" LOC="N4" | IOSTANDARD=LVCMOS33 ; // LED2

NET "clk" LOC="N8" | IOSTANDARD=LVCMOS33 ; //
NET "clk" TNM_NET = clk;
TIMESPEC TS_clk = PERIOD "clk" 125 ns HIGH 50%;


In the schematic, i am ussing button 1 which is connected to pin P9 of the fpga chip, i see it has a permanent pull down resistor so... i am guessing this is not floating at all.

the LED2 which i am using has a ground permanent connection, so from the fpga side a HIGH level is required

what is strange i used a simple code just to see if the button really works.... So in my top module i removed the instance of uart4byte moule, and left only the code bellow just to see whats happening

instead of output LD2, i used output reg LD2 so i can assign a value....


always @(posedge clk) begin
if(button == 1) begin
LD2 <=1;
end
else begin
LD2 <=0;

end
so this simple code above is working.... i am beggining to run out of ideeas

- - - Updated - - -

- - - Updated - - -

Hello,

i came across this strange solution, its seems index<=0 was causing some trouble..
i kept getting some warning mesages from ISE 14.7

Due to other FF/Latch trimming, FF/Latch <index_1> has a constant value of 0 in block <uart4byte>. This FF/Latch will be trimmed during the optimization process.

Code:
   if(index < 7) begin // check to see if we sent all 8 data bits 
					          		  index <= index +1'd1;//increment by 1
					                 state <= send; // set next state for sending remaining bits
					               end
							    else begin // if we sent all the data bits do this... 
							           [COLOR="#FF0000"]index <=0 [/COLOR]; // clear the index counter
							           state <= stop; // set next state for sending the stop bit
							    end
							 end

So i remove that instance of index and moved it bellow in the code, and there is no more warning, and the hardware works !
Code:
	                               if((index+pos)== 31) begin
						  	pos<=8'd0;
							state <= idle; // set next state for clearing the data line
						  end
				       else begin
						   state<=start; // back to start
						   pos <=pos + 8'd8; // increment by 8positions	
                                                  [COLOR="#008000"] index<=0;[/COLOR]							
				       end

Since i am not a experienced guy in HDL programing, why is this diference since from the logical point of view both should do the same thing?
 

Attachments

  • cmods6_sch.pdf
    338.4 KB · Views: 73

Hi,

No schematic for switch connection.

Klaus
 

The problem in your code was a logic issue.

Code:
    send: //3
      begin
      tx_out <= data[index+pos];
      if(index < 7) begin // check to see if we sent all 8 data bits 
        index <= index +1;//increment by 1
        state <= send; // set next state for sending remaining bits
      end else begin // if we sent all the data bits do this... 
        [COLOR="#FF0000"]index <=0[/COLOR] ; // clear the index counter[COLOR="#FF0000"]You clear this when exiting the state and the index was 7, but now becomes 0[/COLOR]
        state <= stop; // set next state for sending the stop bit
      end
      end

Code:
    clear: 
      begin
      tx_out<=1'b1; // set the dataline to high, indicating a stop bit [COLOR="#FF0000"]Not sure about this I thought your intention was to clear the tx_out in this state?[/COLOR]
      if(([COLOR="#FF0000"]index+pos[/COLOR])== 31) begin [COLOR="#FF0000"]// index+pos can never be equal to 31 as index is always 0 from the above exit condition. Iff you had instead made this comparison pos == 24 it would have worked correctly[/COLOR]
        pos<=0;
        state <= idle; // set next state for clearing the data line
      end else begin
        state<=start; // back to start
        pos <=pos + 8; // increment by 8positions   
      end
 

Hello adsee, thanks for you remark...

I still have a question since i am new in verilog regarding always blocks... i still have trouble in code exectuions...

If i want to use "enable" signal in if else inside a always block, its mandatory that "enable" should be present in the sensitivity list of the always block? like this
Code:
always @(posedge clock or enable)

Variant 1
Code:
input enable,
output reg [31:0] count 

always @(posedge clock) begin

   if(enable == 1) begin
      count <= count + 32'd1;
   end
   else begin
      count<=0;
   end
end


or
Variant2
Code:
input enable,
output reg [31:0] count 

always @(posedge clock or enable) begin

   if(enable == 1) begin
      count <= count + 32'd1;
   end
   else begin
      count<=0;
   end
end

which is the corect code variant?

Thanks
 

The first code sample implements a synchronous enable.
The second implements an asynchronous enable (it may or may not synthesize correctly, I haven't checked).

Besides the posedge clock, the only other signal you can or should include is an asynchronous reset either posedge reset (for an active high reset) or negedge reset (for an active low reset).

For combonational logic use always @ (*) or always @* to avoid missing something in the sensitivity list.

You should always stay aware of the fact you are describing hardware and FFs only update on clock edges or when asynchronous inputs like Reset and Set pins are active. Other inputs like Data and Enable are synchronous.
 

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