Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

$recovery error in post-synthesis simulation

Status
Not open for further replies.
I

inputoutput

Member level 1
Joined
Mar 18, 2017
Messages
32
Helped
2
Reputation
4
Reaction score
2
Trophy points
8
Activity points
231
I am running a gate level simulation with SDF and I'm getting error messages such as Error: $recovery( posedge RN:591154 ps, posedge CP &&& D:785400 ps, 194343 ps );. Functional simulation works okay however output of SDF simulation is "XXX". What does the $recovery error mean?

Update

Okay I have reduced the clock frequency even further, from over 100 MHz to about 10 MHz and the timing simulation is showing some outputs, even though at other times it is still showing "XXX". But now I get "Bad $recrem constraints: 10 ps and -67 ps. Negative limit(s) set to zero." errors. Synthesis reported no setup or hold violations.
 
Last edited:

where are these messages coming from? I assume from the gate-level description of the standard cell library. Check their documentation, they might have default values for these that are too aggressive. Or you are simulating things at the wrong 'frequency'.
 

ThisIsNotSam said:
where are these messages coming from? I assume from the gate-level description of the standard cell library. Check their documentation, they might have default values for these that are too aggressive. Or you are simulating things at the wrong 'frequency'.
Click to expand...

Thanks for your reply. Check my updated post. The $recovery error messages is with respect to the cell library.
 

inputoutput said:
Thanks for your reply. Check my updated post. The $recovery error messages is with respect to the cell library.
Click to expand...

Check the verilog file they provided and see how recovery was defined. Compare whatever time unit they are using with your `timescale and with your simulation clock period. This type of error happens a lot in unit delay type of simulations if you are not careful.
 

inputoutput said:
I am running a gate level simulation with SDF and I'm getting error messages such as Error: $recovery( posedge RN:591154 ps, posedge CP &&& D:785400 ps, 194343 ps );. Functional simulation works okay however output of SDF simulation is "XXX". What does the $recovery error mean?
Click to expand...

Reference this for recovery check.

It seems really strange that the numbers in the above Error are 591.154 ns 785.4 ns and 194.343 ns. I've never seen such large values for a recovery check before. seems like they should have been in fs so they would end up as 591 ps, 785 ps and 194 ps which would make a lot more sense.
 
ads-ee said:
Reference this for recovery check.

It seems really strange that the numbers in the above Error are 591.154 ns 785.4 ns and 194.343 ns. I've never seen such large values for a recovery check before. seems like they should have been in fs so they would end up as 591 ps, 785 ps and 194 ps which would make a lot more sense.
Click to expand...

Exactly. OP is not defining "time" correctly in his testbench.
 

I think I was getting the error because I accidentally had hdlin_ff_always_sync_set_reset set to true although I was using an asynchronous reset. Setting this to false appears to fix the problem. However I have another problem. The design is only working 100% correctly with a very low frequency 10MHz. However, the timing analysis in design compiler shows that the circuit should run at more than 100MHz. What could be the reason for this?

@ads-ee Thanks for the link to recovery and removal. It was useful.
 

inputoutput said:
I think I was getting the error because I accidentally had hdlin_ff_always_sync_set_reset set to true although I was using an asynchronous reset. Setting this to false appears to fix the problem. However I have another problem. The design is only working 100% correctly with a very low frequency 10MHz. However, the timing analysis in design compiler shows that the circuit should run at more than 100MHz. What could be the reason for this?

@ads-ee Thanks for the link to recovery and removal. It was useful.
Click to expand...

check all of your wait statements in your testbench. make sure they are respecting the clock frequency you want. other than that, what happens at 100mhz? are you getting setup or hold violations?
 
ThisIsNotSam said:
check all of your wait statements in your testbench. make sure they are respecting the clock frequency you want. other than that, what happens at 100mhz? are you getting setup or hold violations?
Click to expand...

Yes, I do get a "Scheduled event on delay net was cancelled." warning at 100 MHz. The design shows some output and some X's as well at 100 MHz even though the outputs are incorrect.
 

The problem was the asynchronous reset wasn't properly synchronized with my flip flops causing recovery errors. This works well now at the given frequency. Thanks for all the help!
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top