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  1. #1
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    Does clock latency always have to be reduced

    Does the source latency (Not the network) have to be reduced in all designs or are there any cases where higher source latency actually happens to be good for the design.

    •   Alt15th April 2017, 20:29

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  2. #2
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    Re: Does clock latency always have to be reduced

    It is better to be as short as possible, to reduce the power consumption with less cell.
    In practical design, clock devider modules usually placed near the PLL output.
    Lenthening the clock source delay is rarely found.
    To improve one's brain, the doors are needed over the keys.



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