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  1. #1
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    Verilog Programming problem

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    Code:
    `timescale 100ns/1ps
    
    module CarryLAS_tb;
    
    reg [7:0] a;
    reg [7:0] b;
    reg ci;
    
    wire [7:0] sum;
    wire of; //overflow
    wire co;
    
    integer i;
    
    CarryLAS_8 CLA(a,b,ci,sum,co,of);   
    
    
    
    initial begin 
    
    a=0;
    b=0;
    ci=0;
    
    end
    
    
    initial begin // all possible cases 
    
    for(i=0; i<262144; i=i+1) // 2^18
    
    
    #10 {a, b, ci} = i;
    
    
    end
    
    endmodule
    
    module CarryLAS_8(a,b,ci,sum,co,of);
    
    input [7:0] a,b;
    
    input ci; // 0; Add 1: Subtract
    
    output [7:0] sum;
    output co;
    output of;
    
    wire[7:0] c;
    
    wire[7:0] xb;
    
    xor(xb[0],b[0],ci);
    
    xor(xb[1],b[1],ci);
    
    xor(xb[2],b[2],ci);
    
    xor(xb[3],b[3],ci);
    
    xor(xb[4],b[4],ci);
    
    xor(xb[5],b[5],ci);
    
    xor(xb[6],b[6],ci);
    
    xor(xb[7],b[7],ci);
    
    xor(of,c[7],c[6]);
    
    xor(co,c[7],ci);
    
    CarryLA_8 CLAS(a,xb,ci,sum,co);
    
    
    endmodule
    
    
    module CarryLA_8(a,b,ci,sum,co);
    
    input [7:0] a,b;
    input ci;
    
    output [7:0] sum;
    output co;
    
    wire [7:0] sum;
    wire cm,co;
    
    CarryLA_4 CLA0(a[3:0],b[3:0],ci,sum[3:0],cm);
    CarryLA_4 CLA1(a[7:4],b[7:4],cm,sum[7:4],cm);
    
    endmodule
    
    
    module CarryLA_4(a,b,ci,sum,co);
    
    input [3:0] a,b;
    
    input ci; // 0; Add 1: Subtract
    
    output [3:0] sum;
    
    output co;
    
    wire[3:0] g,p,cout;
    wire G0,P0;
    wire[9:0] w;
    
    and a0(g[0],a[0],b[0]); 
    and a1(g[1],a[1],b[1]); 
    and a2(g[2],a[2],b[2]); 
    and a3(g[3],a[3],b[3]); 
    
    
    xor x0(p[0],a[0],b[0]);
    xor x1(p[1],a[1],b[1]);
    xor x2(p[2],a[2],b[2]);
    xor x3(p[3],a[3],b[3]);
    
    and and0(w[0],p[0],ci);
    or or0(cout[0],g[0],w[0]);
    
    and and1(w[1],p[1],p[0],ci);
    and and2(w[2],p[1],g[0]);
    or or1(cout[1],g[1],w[2],w[1]);
    
    and and3(w[3],p[2],p[1],p[0],ci);
    and and4(w[4],p[2],p[1],g[0]);
    and and5(w[5],p[2],g[1]);
    or or2(cout[2],g[2],w[5],w[4],w[3]);
    
    and and6(w[6],p[3],p[2],p[1],g[0]);
    and and7(w[7],p[3],p[2],g[1]);
    and and8(g[2],a[2],b[2]); 
    or or3(G0,g[3],w[8],w[7],w[6]);
    
    and and9(P0,p[3],p[2],p[1],p[0]);
    
    and and10(w[9],P0,ci);
    or or4(cout[3],G0,w[9]);
    
    and and11(co,cout[3],1);
    
    xor xor0(sum[0],p[0],ci);
    xor xor1(sum[1],p[1],cout[0]);
    xor xor2(sum[2],p[2],cout[1]);
    xor xor3(sum[3],p[3],cout[2]);
    
    
    
    endmodule

    This is my Verilog code. simulated well, but the result kinda sucks. 'sum' produces values with some Xs, and 'co', 'of'(overflow detection) are also Xs. I couldn't find out what the problem is. It might be about carry I think. Could anyone help me with this? Any help would be really appreciated. Thanks in advance.

    Captured waveform is attached

    •   Alt14th April 2017, 19:23

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  2. #2
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    Re: Verilog Programming problem

    By inspection (of module CarryLA_4) you have nothing driving w[8]. You have shorted g[2] on instance a2 and and8. and8 was probably supposed to be driving w[8] would be my guess.

    What is up with schools that teach you how to use Verilog by making you use the builtin gate primitives. That is really stupid, you'll never use this after you get out of school. This is a stupid assignment, and you can show your teacher my post .

    - - - Updated - - -

    They really should teach you useful stuff, like using Verilog 2001 module port syntax and using named association for ports on a instantiated module instead of positional association.


    1 members found this post helpful.

    •   Alt14th April 2017, 21:14

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  3. #3
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    Re: Verilog Programming problem

    I solved it on my own, but thanks a lot anyway! you're right. w[8] was the problem.



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