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    VHDL - generate signals from other signals

    Code:
    process(rst, adcclock_80Mhz)
      begin
         if rst = '1' then
            ADC_Timelog <= (others => '0');
    		  ADC_Timecnt <= 0;
    		  
    	  elsif adcclock_80Mhz'event and adcclock_80Mhz = '1' then
    			ADC_Timecnt <= ADC_Timecnt + 1;
    			time_ack <= '0';
    				if(ADC_Timecnt = 8192) then 		
    				ADC_Timelog <= ADC_Timelog + '1';
    				Timestamp <= "11" & "00" & cal1 & cal2 & ADC_Timelog;
    				time_ack <= '1';
    				ADC_Timecnt <= 0;
    				end if;
    				if time_ack='1' then
    					timelog1 <= timelog1+1;
    				        timelog2 <= timelog2+1;
    
    						if timelog1 < 64 then
    								cal1 <= '1'; 
    								elsif timelog1 > 64 and timelog1 < 128 then 
    								cal1 <= '0';
    								elsif timelog1 > 128 then
    								timelog1 <=0;
    						end if;
    				
    						if timelog2 < 32 then
    							cal2 <='1'; 
    							elsif timelog2 > 32 and timelog2 < 64 then 
    							cal2 <='0';
    							elsif timelog2 > 64 then
    							timelog2 <=0;
    						end if;
    				end if;
    end if;
    end process;

    I am trying to generate two signals one that will be twice the frequency of the other from the signal time_ack, The code generates the two signals cal1 and cal2, but I see a phase difference between cal1 and cal2 and that is varying with time. Am I doing anything wrong generating these signals this way?

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    Re: VHDL - generate signals from other signals

    Can you sketch the intended waveform?



    •   Alt14th April 2017, 18:35

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  3. #3
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    Re: VHDL - generate signals from other signals

    adc_clock80MHz is an 80MHz clock signal; First I count this clock and when it reaches 8192 I keep time_ack=1 for 1 clock cycle of the adc_clock80MHz. Now I count time_ack using timelog1 and timelog2. When timelog1 is below 64 I keep cal1 as 1 and if it is between 64 and 128 I make it 0 and above 128 I make timelog1 zero so that the whole cycle can continue. Similarly for timelog2 and cal2 excpet it is 64 and 32 instead of 128 and 64.

    Finally the 26 bit data ADC_Timelog, cal1 and cal2 are supplemented with 1100 as header bits and pushed out as a 32 bit data.
    Last edited by arve9066; 14th April 2017 at 19:02.



    •   Alt14th April 2017, 18:55

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    Re: VHDL - generate signals from other signals

    What are the actual period intervals that you want, I think your counters are all cycling on the wrong values, I ran your code and you need to fix your code and add adc_timelog1/2 to the reset.

    Your counters are really badly written too. IMO a counter should implement a register who's output is fed back to an add 1 and a compare to terminal count. The compare is used as a select to a mux to either load the add 1 or a 0. I really don't like counter code where someone relies on the language rules for assignment ordering instead of explicitly defining what happens when using an if-elsif-end if structure.

    You also seem to have problems with knowing how to count and how to compare count values so things line up properly. I bet you want to have the time_ack pulse with a period of 8192 instead of 8193 like you have done (like I said, you need to learn how to count). FYI if you want to count to ten as a human you count like this: 1,2,3,4,5,6,7,8,9,10, but if you are a piece of silicon and you want to count using binary you'll probably count to ten like this: 0,1,2,3,4,5,6,7,8,9. Notice any differences?

    Due to your counting problems you are setting and clearing the bits at the wrong time out of phase with each other as the counters timelog1 and timelog2 are not synchronized with each other. timelog1 cycles on 130 counts, and timelog2 cycles on 66 counts, as you can see these two numbers are not a 2:1 ratio.

    Learn how to count and how to write a proper counter. Just look for posts on this subject, I've mentioned how to count correctly on multiple threads.


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    •   Alt14th April 2017, 20:14

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    Re: VHDL - generate signals from other signals

    I need to have 8192 samples of ADC data between two samples of time which I do get with this code. So I do not think there is a counting problem in that part of code. I count from 0 to 8191 which gives me 8192 samples and at the 8193rd sample I make the time_ack=1 and set counter ADC_Timecnt=0. So I get 8192 samples of ADC data between two samples of time data.

    I added the cal1 and cal2 later to generate two signals which are derived from time_ack with one twice the frequency of other, I used 64 and 128 as just test case. I realise there are counting issues on that and I am trying to iron that out and how to make it right.



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    Re: VHDL - generate signals from other signals

    Quote Originally Posted by arve9066 View Post
    I need to have 8192 samples of ADC data between two samples of time which I do get with this code. So I do not think there is a counting problem in that part of code. I count from 0 to 8191 which gives me 8192 samples and at the 8193rd sample I make the time_ack=1 and set counter ADC_Timecnt=0. So I get 8192 samples of ADC data between two samples of time data.
    Your time_ack cycle time repeat interval is therefore 8193 ADC clock cycles, but that wasn't apparent with your code (since you have no comments).

    You know there are easier ways to make the two cal1 and cal2 signals that is less of an ugly and error prone set of if statements. for the faster cal signal generate a counter that cycles at the half period (I guess that was 32 in your case?). Count 0-31, on 31 toggle that caln signal (i.e. caln <= NOT caln). on either a count of 31 and that caln signal either '0' or '1' depending on the alignment of the signals you want, toggle calm <= NOT calm. That is a lot simpler to follow and requires only a single counter.


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    Re: VHDL - generate signals from other signals

    I did not fully understand the method you have specified. Could you explain a bit more so that I can understand it better. I am pretty new to this as you could guess..

    Also I do understand that the if statement implementation is not the pretty way of doing it, but if I get the numbers in it right 63, 64, 127 or 128, theoretically it should work right without the phase delay ( or no? )



    •   Alt18th April 2017, 19:29

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  8. #8
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    Re: VHDL - generate signals from other signals

    Quote Originally Posted by arve9066 View Post
    I did not fully understand the method you have specified. Could you explain a bit more so that I can understand it better. I am pretty new to this as you could guess..

    Also I do understand that the if statement implementation is not the pretty way of doing it, but if I get the numbers in it right 63, 64, 127 or 128, theoretically it should work right without the phase delay ( or no? )
    Yeah if you get them right, the operative word is IF you get them right. Unless you really good at writing if statements that cover all the possible cases then you are better off not writing synchronized counters using such complicated if statements and just use the KISS (Keep It Simple S-------) rule

    e.g.
    Code:
                    3       3       3       3
    counter: 0 .... 10 .... 10 .... 10 .... 1
                     ________        ________
    cal_a:   ________11111111________11111111
                    ^       ^ - toggle cal_a on counts of 31
                             ________________
    cal_b:   ________________1111111111111111
                            ^ - toggle cal_b on count of 31 when cal_a is 1
                     ________________
    cal_b:   ________1111111111111111________
                    ^               ^ - toggle cal_b on count of 31 when cal_a is 0
    Depends on which alignment you want for choosing cal_b option 1 or 2

    Yes you could use the counter bits directly if you want, but that doesn't let you instead do this for say a count of 18 (0-17).


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    Re: VHDL - generate signals from other signals

    I did get the thing working by getting the numbers right. I have no phase lag now between the two signals. But I will implement the same using counters as it seems the right way of doing it. Thank you very much for the suggestion.



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