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13th April 2017, 20:06 #1
- Join Date
- Jul 2009
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4byte data is not flowing between two modules in verilog
i am a bit new in verilog... i have in my top module two other modules instatiated, the problem is when i try to send data from counter to uart, on the logic analyzer connected to uart line, i read 00 00 00 00
The data out/inputs are declared like bellow
module counter_v2( output reg [31:0] fdata_out ); module uart4byte( input [31:0] data, );
And in the main module i have the two modules instantiated and tied like bellow,
I tryied some debuging for the uart with parameter zzz[31:0] = 32'h AABBCCDD and this way it works.
But if i try to connect data of the uart4bye with the fdata_out its not working. Why?
wire stream; counter_v2 ccc( .fdata_out(stream) ); uart4byte uuu( .data(stream), );
Last edited by moro; 13th April 2017 at 20:22.
13th April 2017, 20:06
13th April 2017, 23:34 #2
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- Sep 2013
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Re: 4byte data is not flowing between two modules in verilog
Why are you using a single bit
to represent a 32-bit connection from fdata_out to data?Code:wire stream;